FPGA让数码管亮起来

最新推荐文章于 2023-04-26 16:33:58 发布

victorzheng2012

最新推荐文章于 2023-04-26 16:33:58 发布

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分类专栏：一步一步学FPGA

本文链接：https://blog.csdn.net/victorzheng2012/article/details/8769783

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这段代码展示了如何使用FPGA来控制数码管显示。通过一个进程process处理时钟信号，实现了数码管的动态扫描和计数器更新，使得数码管能够按照预定的数值和间隔时间亮起。代码中定义了常量data存储了0-9对应的段码，并使用CONV_STD_LOGIC_VECTOR转换函数将整数转换为适合数码管显示的位矢量。

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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--use ieee.std_logic_1164.all;
entity led is
	port(
	clk:in std_logic;
		seg:out std_logic_vector(2 downto 0);
		duan:out std_logic_vector(7 downto 0)
	);
end entity;
architecture behavor of led is
type ram1 is array(0 to 9) of std_logic_vector(7 downto 0);
constant data:ram1 :=("01000000","01111001","00100100","00110000","00011001","00010010","00000010","01111000","00000000","00010000");--共阳极数码管对应0-9数字段值
signal n1,n2,n3,n4,n5:integer range 0 to 1000;
begin
seg<=CONV_STD_LOGIC_VECTOR( n5,3); --运用一个转换函数将整数转换为一个3位的位矢量
	process(clk)--duan kongzhi jincheng
	begin
	if clk'event and clk='1' then
		if n1<1000 then
			n1<=n1+1;
			else if n2<1000 then
				 n2<=n2+1;
				 n1<=0;
				 else if n