FPGA VERILOG解析SV报文

主要模块

1）GMII_TO_RGMII模块，实现RGMII和GMII接口的转换

2）SV模块，实现SV报文的解析

3）CRC模块，实现接收帧的CRC校验

4）SYSTEM_ILA模块，用于调试

5）CLK_WIZ模块，供原语200MHz的时钟，和ILA125MHz的时钟

该程序用于验证SV解析代码的正确性。

SV解析模块

SV解板模块的输入输出如下，本机MAC、APPID、SVID以及电流、电压的通道可以自定义。

module sv #(
    parameter              MAC =  48'h01_0c_cd_01_00_01,
    parameter              APPID = 16'h4000,
    parameter [33*8-1:0]   SVID = "MB5012BMU/LLN0.smvcb0",
    parameter              CHUA = 8'd0,
    parameter              CHUB = 8'd1,
    parameter              CHUC = 8'd2,
    parameter              CHIA = 8'd3,
    parameter              CHIB = 8'd4,
    parameter              CHIC = 8'd5
)
(
    input                   rst_n,
    input                   gmii_rx_clk,
    input                   gmii_rx_dv,
    input [7:0]             gmii_rxd,
    input [31:0]            gmii_rxd_crc,
    
    output reg              crc_en,
    output reg              crc_clr,
    output reg              data_valid,
    
    output reg [31:0]       ua,
    output reg [31:0]       ub,
    output reg [31:0]       uc,
    output reg [31:0]       ia,
    output reg [31:0]       ib,
    output reg [31:0]       ic
);

状态机设置

代码采用一段式状态机，涵盖SV报文的每个字段，针对可选项和多个ASDU的场景亦可处理。

localparam  st_idle                                     = 8'd0; //初始状态，等待接收前导码
localparam  st_preamble                                 = 8'd1; //接收前导码状态
localparam  st_delimiter                                = 8'd2;
localparam  st_header_desmac                            = 8'd3;
localparam  st_header_srcmac                            = 8'd4;
localparam  st_priority_tpid_or_ethtype                 = 8'd5;
localparam  st_priority_tci                             = 8'd6;

localparam  st_ethtype_with_priority                    = 8'd7;
localparam  st_header_appid                             = 8'd8;
localparam  st_header_length                            = 8'd9;
localparam  st_header_res                               = 8'd10;

localparam  st_apdu_start                               = 8'd11;
localparam  st_apdu_len                                 = 8'd12;
localparam  st_asdu_start                               = 8'd13;
localparam  st_asdu_len                                 = 8'd14;
localparam  st_asdu_sub                                 = 8'd15;
localparam  st_asdu_sub_len                             = 8'd16;
localparam  st_asdu_svid_len                            = 8'd17;
localparam  st_asdu_svid_val                            = 8'd18;
localparam  st_asdu_dataset_or_smpcnt                   = 8'd19;
localparam  st_asdu_dataset_without_tag                 = 8'd20;
localparam  st_asdu_smpcnt_with_dataset_with_tag        = 8'd21;
localparam  st_asdu_smpcnt_without_dataset_without_tag  = 8'd22;

localparam  st_asdu_confrev                             = 8'd23;
localparam  st_asdu_refrtm_or_smpsync                   = 8'd24;
localparam  st_asdu_refrtm_without_tag                  = 8'd25;
localparam  st_asdu_smpsync_with_refrtm_with_tag        = 8'd26;
localparam  st_asdu_smpsync_without_refrtm_without_tag  = 8'd27;

localparam  st_asdu_smprate_or_smpvlen                  = 8'd28;
localparam  st_asdu_smprate_without_tag                 = 8'd29;
localparam  st_asdu_smpvlen_with_smprate_with_tag       = 8'd30;
localparam  st_asdu_smpvlen_without_smprate_without_tag = 8'd31;
localparam  st_asdu_smpvlen_len                         = 8'd32;
localparam  st_asdu_data                                = 8'd33;
localparam  st_crc                                      = 8'd34;

localparam  st_end                                      = 8'd255;

模拟SV数据，通道1是10000

ILA抓包数据

工程代码若有需要，可留言联系。