ra8876中文规格书_RA8876 Datasheet(数据表) 10 Page - RAIO Technology Inc.

Brief Datasheet

Character/Graphic TFT LCD Controller

RAiO TECHNOLOGY INC.

10

/14

www.raio.com.tw

RA8876

4.2

Serial Host Interface (Multiplex with Parallel Host Interface)

Pin Name

Dir/Drv.

Pin Description

XSSCL

(XDB[7])

I

SPI or IIC Clock

XSSCL, 3-wire, 4-wire Serial or IIC I/F clock.

XSSDI

XSSDA

(XDB[6])

I

IIC data /4-wire SPI Data Input

3-wire SPI I/F: NC, please connect it to GND.

4-wire SPI I/F: XSSDI, Data input for serial I/F.

IIC I/F: XSSDA, Bi-direction data for serial I/F

XSSD

XSSDO

(XDB[5])

IO

3-wire SPI Data /4-wire SPI Data Output/IIC Slave Address Select

3-wire SPI I/F: XSSD, Bi-direction data for serial I/F

4-wire SPI I/F: XSSDO, Data output for serial I/F.

IIC I/F: XIICA[5], IIC device address bit [5]

XnSCS

(XDB[4])

I

SPI Chip Select/IIC Slave Address Select

XnSCS, Chip select pin for 3-wire or 4-wire serial I/F.

IIC I/F : XIICA[4], IIC device address bit [4].

XIICA[3:0]

(XDB[3:0])

I

IIC I/F: IIC Slave Address Select.

XIICA[3:0], 3|4-wire SPI I/F: NC, please connect it to GND.

IIC I/F : IIC device address bit [3:0]

4.3

SDR SDRAM Interface (39 signals)

Pin Name

Dir/Drv.

Pin Description

XMCKE

(XCLK2)

IO

(8mA)

Clock enable / Clock 2 input (memory clock)

When XTEST[0] set low, this pin is SDR memory clock enable

When XTEST[0] set high, this pin is external clock 2 input for SDR access.

XMCLK

IO

(8mA)

SDR memory Clock out

It derives from MPLL or XCLK2

XnMCS

O

(4mA)

Chip select

XnMRAS

O

(4mA)

Command outputs: XnMRAS, XnMCAS and XnMWR (along with XnMCS)

define the command being entered

XnMCAS

O

(4mA)

Command outputs

XnMWR

O

(4mA)

Command outputs

XMBA[1:0]

O

(4mA)

Bank address

XMA[12:0]

O

(4mA)

Address

XMD[15:0]

I/O

(4mA)

Data bus.

XMDQM[1:0]

O

(4mA)

Input/Output mask