VHDL 等占空比5分频电路

--等占空比5分频电路

--div_5.vhd file

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY div_5 IS
    PORT(clk_in:IN std_logic;
         clk_out:OUT std_logic
    );
END div_5;

ARCHITECTURE rtl OF div_5 IS
  SIGNAL clk_up,clk_down:std_logic;
  SIGNAL count_up,count_down: INTEGER:= 0;
BEGIN
  clk_out <= clk_up and clk_down;

  PROCESS(clk_in)
    BEGIN

    IF (clk_in'event and clk_in = '1') THEN
        IF(count_up < 4) THEN
            count_up <= count_up + 1;
        ELSE
            count_up <= 0;
        END IF;
    END IF;
  END PROCESS;

  PROCESS(clk_in)

  BEGIN
    IF(clk_in'event and clk_in = '0') THEN
        IF(count_down < 4) THEN
            count_down <= count_down + 1;