占空比50%，5次分频器，VHDL语言设计

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity div is
port(clk:in std_logic; k_or,k1,k2:out std_logic);
end;
architecture bhv of div is
signal c1,c2:std_logic_vector(2 downto 0);
signal m1,m2:std_logic;
begin
process (clk,c1) begin
if rising_edge(clk) then
if (c1="100") then c1<="000"; else c1<=c1+1;end if;
if (c1="001") then m1<=not m1; elsif (c1="011") then m1<=not m1;end if;
end if;
end process;
process (clk,c2) begin
 if falling_edge(clk ) then 
 if (c2 = "100") then c2<="000" ; else c2<=c2+1 ; end if;
 if (c2="001") then m2<=not m2 ; elsif (c2="011") then m2<=not m2;
 end if; end if;
 end process;
 k1 <=m1; k2<=m2;k_or <=m1 or m2;
 end bhv;