五分频电路(50%占空比)
设计代码
`timescale 1ns / 1ps
//
// Company:
// Engineer:
//
// Create Date: 20:28:43 05/10/2020
// Design Name:
// Module Name: five_fp
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//
module five_fp(
input clk,
input rst,
output fclk,
output reg[2:0] cnt
);
always@(posedge clk or negedge rst)
begin
if(~rst)
begin
cnt <= 0;
end
else if(cnt == 4)
begin
cnt <= 0;
end
else
cnt <= cnt + 1;
end
reg f1clk,f2clk;
always@(posedge clk or negedge rst)
begin
if(~rst)
begin
f1clk <= 1;
end
else if(cnt == 1)
begin
f1clk <= ~f1clk;
end
else if(cnt ==