这篇博客主要探讨了在N76e003单片机上如何将系统时钟从内部时钟切换到外部时钟，由于N76e003不支持无源晶振且有源晶振成本较高，相关资料稀缺。作者通过代码示例展示了具体的配置过程。
N76e003切换到外部时钟的资料很少(因为N76e003的片子是不支持无源晶振的，有源晶振的成本又很高，所以网上很少有对N76e003的介绍)。有图有真相：
代码如下：
main.c
1 #include <N76E003.H> 2 #include <SFR_Macro.h> 3 #include <Function_Define.h> 4 5 bit BIT_TMP; // 调用 SFR_Macro.h 使用的 6 7 void main(void){ 8 // 开通外部 9 set_EXTEN1; 10 set_EXTEN0; 11 // 等待外部稳定 12 while(!(CKSWT|0x08)); 13 // 选择外部时钟 14 clr_OSC1; 15 set_OSC0; 16 // 等待外部时钟切换成功 17 while(CKEN&0x01); 18 while(1){ 19 ; // 函数主题 20 } 21 }
1 /*-------------------------------------------------------------------------- 2 N76E003.H 3 4 Header file for Nuvoton N76E003 5 --------------------------------------------------------------------------*/ 6 7 #ifndef __N76E885_H__ 8 #define __N76E885_H__ 9 10 sfr P0 = 0x80; 11 sfr SP = 0x81; 12 sfr DPL = 0x82; 13 sfr DPH = 0x83; 14 sfr RWK = 0x86; 15 sfr PCON = 0x87; 16 17 sfr TCON = 0x88; 18 sfr TMOD = 0x89; 19 sfr TL0 = 0x8A; 20 sfr TL1 = 0x8B; 21 sfr TH0 = 0x8C; 22 sfr TH1 = 0x8D; 23 sfr CKCON = 0x8E; 24 sfr WKCON = 0x8F; 25 26 sfr P1 = 0x90; 27 sfr SFRS = 0x91; //TA Protection 28 sfr CAPCON0 = 0x92; 29 sfr CAPCON1 = 0x93; 30 sfr CAPCON2 = 0x94; 31 sfr CKDIV = 0x95; 32 sfr CKSWT = 0x96; //TA Protection 33 sfr CKEN = 0x97; //TA Protection 34 35 sfr SCON = 0x98; 36 sfr SBUF = 0x99; 37 sfr SBUF_1 = 0x9A; 38 sfr EIE = 0x9B; 39 sfr EIE1 = 0x9C; 40 sfr CHPCON = 0x9F; //TA Protection 41 42 sfr P2 = 0xA0; 43 sfr AUXR1 = 0xA2; 44 sfr BODCON0 = 0xA3; //TA Protection 45 sfr IAPTRG = 0xA4; //TA Protection 46 sfr IAPUEN = 0xA5; //TA Protection 47 sfr IAPAL = 0xA6; 48 sfr IAPAH = 0xA7; 49 50 sfr IE = 0xA8; 51 sfr SADDR = 0xA9; 52 sfr WDCON = 0xAA; //TA Protection 53 sfr BODCON1 = 0xAB; //TA Protection 54 sfr P3M1 = 0xAC; 55 sfr P3S = 0xAC; //Page1 56 sfr P3M2 = 0xAD; 57 sfr P3SR = 0xAD; //Page1 58 sfr IAPFD = 0xAE; 59 sfr IAPCN = 0xAF; 60 61 sfr P3 = 0xB0; 62 sfr P0M1 = 0xB1; 63 sfr P0S = 0xB1; //Page1 64 sfr P0M2 = 0xB2; 65 sfr P0SR = 0xB2; //Page1 66 sfr P1M1 = 0xB3; 67 sfr P1S = 0xB3; //Page1 68 sfr P1M2 = 0xB4; 69 sfr P1SR = 0xB4; //Page1 70 sfr P2S = 0xB5; 71 sfr IPH = 0xB7; 72 sfr PWMINTC = 0xB7; //Page1 73 74 sfr IP = 0xB8; 75 sfr SADEN = 0xB9; 76 sfr SADEN_1 = 0xBA; 77 sfr SADDR_1 = 0xBB; 78 sfr I2DAT = 0xBC; 79 sfr I2STAT = 0xBD; 80 sfr I2CLK = 0xBE; 81 sfr I2TOC = 0xBF; 82 83 sfr I2CON = 0xC0; 84 sfr I2ADDR = 0xC1; 85 sfr ADCRL = 0xC2; 86 sfr ADCRH = 0xC3; 87 sfr T3CON = 0xC4; 88 sfr PWM4H = 0xC4; //Page1 89 sfr RL3 = 0xC5; 90 sfr PWM5H = 0xC5; //Page1 91 sfr RH3 = 0xC6; 92 sfr PIOCON1 = 0xC6; //Page1 93 sfr TA = 0xC7; 94 95 sfr T2CON = 0xC8; 96 sfr T2MOD = 0xC9; 97 sfr RCMP2L = 0xCA; 98 sfr RCMP2H = 0xCB; 99 sfr TL2 = 0xCC; 100 sfr PWM4L = 0xCC; //Page1 101 sfr TH2 = 0xCD; 102 sfr PWM5L = 0xCD; //Page1 103 sfr ADCMPL = 0xCE; 104 sfr ADCMPH = 0xCF; 105 106 sfr PSW = 0xD0; 107 sfr PWMPH = 0xD1; 108 sfr PWM0H = 0xD2; 109 sfr PWM1H = 0xD3; 110 sfr PWM2H = 0xD4; 111 sfr PWM3H = 0xD5; 112 sfr PNP = 0xD6; 113 sfr FBD = 0xD7; 114 115 sfr PWMCON0 = 0xD8; 116 sfr PWMPL = 0xD9; 117 sfr PWM0L = 0xDA; 118 sfr PWM1L = 0xDB; 119 sfr PWM2L = 0xDC; 120 sfr PWM3L = 0xDD; 121 sfr PIOCON0 = 0xDE; 122 sfr PWMCON1 = 0xDF; 123 124 sfr ACC = 0xE0; 125 sfr ADCCON1 = 0xE1; 126 sfr ADCCON2 = 0xE2; 127 sfr ADCDLY = 0xE3; 128 sfr C0L = 0xE4; 129 sfr C0H = 0xE5; 130 sfr C1L = 0xE6; 131 sfr C1H = 0xE7; 132 133 sfr ADCCON0 = 0xE8; 134 sfr PICON = 0xE9; 135 sfr PINEN = 0xEA; 136 sfr PIPEN = 0xEB; 137 sfr PIF = 0xEC; 138 sfr C2L = 0xED; 139 sfr C2H = 0xEE; 140 sfr EIP = 0xEF; 141 142 sfr B = 0xF0; 143 sfr CAPCON3 = 0xF1; 144 sfr CAPCON4 = 0xF2; 145 sfr SPCR = 0xF3; 146 sfr SPCR2 = 0xF3; //Page1 147 sfr SPSR = 0xF4; 148 sfr SPDR = 0xF5; 149 sfr AINDIDS = 0xF6; 150 sfr EIPH = 0xF7; 151 152 sfr SCON_1 = 0xF8; 153 sfr PDTEN = 0xF9; //TA Protection 154 sfr PDTCNT = 0xFA; //TA Protection 155 sfr PMEN = 0xFB; 156 sfr PMD = 0xFC; 157 sfr EIP1 = 0xFE; 158 sfr EIPH1 = 0xFF; 159 160 /* BIT Registers */ 161 /* SCON_1 */ 162 sbit SM0_1 = SCON_1^7; 163 sbit FE_1 = SCON_1^7; 164 sbit SM1_1 = SCON_1^6; 165 sbit SM2_1 = SCON_1^5; 166 sbit REN_1 = SCON_1^4; 167 sbit TB8_1 = SCON_1^3; 168 sbit RB8_1 = SCON_1^2; 169 sbit TI_1 = SCON_1^1; 170 sbit RI_1 = SCON_1^0; 171 172 /* ADCCON0 */ 173 sbit ADCF = ADCCON0^7; 174 sbit ADCS = ADCCON0^6; 175 sbit ETGSEL1 = ADCCON0^5; 176 sbit ETGSEL0 = ADCCON0^4; 177 sbit ADCHS3 = ADCCON0^3; 178 sbit ADCHS2 = ADCCON0^2; 179 sbit ADCHS1 = ADCCON0^1; 180 sbit ADCHS0 = ADCCON0^0; 181 182 /* PWMCON0 */ 183 sbit PWMRUN = PWMCON0^7; 184 sbit LOAD = PWMCON0^6; 185 sbit PWMF = PWMCON0^5; 186 sbit CLRPWM = PWMCON0^4; 187 188 189 /* PSW */ 190 sbit CY = PSW^7; 191 sbit AC = PSW^6; 192 sbit F0 = PSW^5; 193 sbit RS1 = PSW^4; 194 sbit RS0 = PSW^3; 195 sbit OV = PSW^2; 196 sbit P = PSW^0; 197 198 /* T2CON */ 199 sbit TF2 = T2CON^7; 200 sbit TR2 = T2CON^2; 201 sbit CM_RL2 = T2CON^0; 202 203 /* I2CON */ 204 sbit I2CEN = I2CON^6; 205 sbit STA = I2CON^5; 206 sbit STO = I2CON^4; 207 sbit SI = I2CON^3; 208 sbit AA = I2CON^2; 209 sbit I2CPX = I2CON^0; 210 211 /* IP */ 212 sbit PADC = IP^6; 213 sbit PBOD = IP^5; 214 sbit PS = IP^4; 215 sbit PT1 = IP^3; 216 sbit PX1 = IP^2; 217 sbit PT0 = IP^1; 218 sbit PX0 = IP^0; 219 220 /* P3 */ 221 sbit P30 = P3^0; 222 223 /* IE */ 224 sbit EA = IE^7; 225 sbit EADC = IE^6; 226 sbit EBOD = IE^5; 227 sbit ES = IE^4; 228 sbit ET1 = IE^3; 229 sbit EX1 = IE^2; 230 sbit ET0 = IE^1; 231 sbit EX0 = IE^0; 232 233 /* P2 */ 234 sbit P20 = P2^0; 235 236 /* SCON */ 237 sbit SM0 = SCON^7; 238 sbit FE = SCON^7; 239 sbit SM1 = SCON^6; 240 sbit SM2 = SCON^5; 241 sbit REN = SCON^4; 242 sbit TB8 = SCON^3; 243 sbit RB8 = SCON^2; 244 sbit TI = SCON^1; 245 sbit RI = SCON^0; 246 247 /* P1 */ 248 sbit P17 = P1^7; 249 sbit AIN0 = P1^7; 250 251 sbit P10 = P1^0; 252 sbit PWM0 = P1^0; 253 sbit P11 = P1^1; 254 sbit PWM1 = P1^1; 255 sbit P12 = P1^2; 256 257 /* TCON */ 258 sbit TF1 = TCON^7; 259 sbit TR1 = TCON^6; 260 sbit TF0 = TCON^5; 261 sbit TR0 = TCON^4; 262 sbit IE1 = TCON^3; 263 sbit IT1 = TCON^2; 264 sbit IE0 = TCON^1; 265 sbit IT0 = TCON^0; 266 267 /* P0 */ 268 sbit P00 = P0^0; 269 sbit INT0 = P0^0; 270 sbit VREF = P0^0; 271 272 sbit P01 = P0^1; 273 sbit INT1 = P0^1; 274 sbit AIN1 = P0^1; 275 276 sbit P02 = P0^2; 277 sbit PWM2 = P0^2; 278 sbit AIN2 = P0^2; 279 280 sbit P03 = P0^3; 281 sbit PWM3 = P0^3; 282 sbit TXD = P0^3; 283 sbit AIN3 = P0^3; 284 285 sbit P04 = P0^4; 286 sbit SS = P0^4; 287 sbit AIN4 = P0^4; 288 289 sbit P05 = P0^5; 290 sbit PWM4 = P0^5; 291 sbit SPICK = P0^5; 292 sbit AIN5 = P0^5; 293 294 sbit P06 = P0^6; 295 sbit SCL = P0^6; 296 sbit AIN6 = P0^6; 297 sbit PWM5 = P0^6; 298 299 sbit P07 = P0^7; 300 sbit AIN7 = P0^7; 301 sbit PWM6 = P0^7; 302 303 304 #endif
1 /**** P0 80H *****/ 2 #define set_P00 P00 = 1 3 #define set_P01 P01 = 1 4 #define set_P02 P02 = 1 5 #define set_P03 P03 = 1 6 #define set_P04 P04 = 1 7 #define set_P05 P05 = 1 8 #define set_P06 P06 = 1 9 #define set_P07 P07 = 1 10 11 #define clr_P00 P00 = 0 12 #define clr_P01 P01 = 0 13 #define clr_P02 P02 = 0 14 #define clr_P03 P03 = 0 15 #define clr_P04 P04 = 0 16 #define clr_P05 P05 = 0 17 #define clr_P06 P06 = 0 18 #define clr_P07 P07 = 0 19 20 //**** SP 81H **** 21 //**** DPH 82H **** 22 //**** DPL 83H **** 23 //**** RWK 86H **** 24 25 //**** PCON 87H ***** 26 #define set_SMOD PCON |= SET_BIT7 27 #define set_SMOD0 PCON |= SET_BIT6 28 #define set_POF PCON |= SET_BIT4 29 #define set_GF1 PCON |= SET_BIT3 30 #define set_GF0 PCON |= SET_BIT2 31 #define set_PD PCON |= SET_BIT1 32 #define set_IDL PCON |= SET_BIT0 33 34 #define clr_SMOD PCON &= ~SET_BIT7 35 #define clr_SMOD0 PCON &= ~SET_BIT6 36 #define clr_POF PCON &= ~SET_BIT4 37 #define clr_GF1 PCON &= ~SET_BIT3 38 #define clr_GF0 PCON &= ~SET_BIT2 39 #define clr_PD PCON &= ~SET_BIT1 40 #define clr_IDL PCON &= ~SET_BIT0 41 42 /**** TCON 88H ****/ 43 #define set_TF1 TF1 = 1 44 #define set_TR1 TR1 = 1 45 #define set_TF0 TF0 = 1 46 #define set_TR0 TR0 = 1 //启动定时器0(定时器0启动控制,0定时器0终止，清除该位将终止定时器0并且当前计数值将保存到TH0和TL0中，1使能定时器0) 47 #define set_IE1 IE1 = 1 48 #define set_IT1 IT1 = 1 49 #define set_IE0 IE0 = 1 50 #define set_IT0 IT0 = 1 51 52 #define clr_TF1 TF1 = 0 53 #define clr_TR1 TR1 = 0 54 #define clr_TF0 TF0 = 0 55 #define clr_TR0 TR0 = 0 56 #define clr_IE1 IE1 = 0 57 #define clr_IT1 IT1 = 0 58 #define clr_IE0 IE0 = 0 59 #define clr_IT0 IT0 = 0 60 61 //**** TMOD 89H **** 62 #define set_GATE_T1 TMOD |= SET_BIT7 63 #define set_CT_T1 TMOD |= SET_BIT6 64 #define set_M1_T1 TMOD |= SET_BIT5 65 #define set_M0_T1 TMOD |= SET_BIT4 66 #define set_GATE_T0 TMOD |= SET_BIT3 67 #define set_CT_T0 TMOD |= SET_BIT2 68 #define set_M1_T0 TMOD |= SET_BIT1 69 #define set_M0_T0 TMOD |= SET_BIT0 70 71 #define clr_GATE_T1 TMOD &= ~SET_BIT7 72 #define clr_CT_T1 TMOD &= ~SET_BIT6 73 #define clr_M1_T1 TMOD &= ~SET_BIT5 74 #define clr_M0_T1 TMOD &= ~SET_BIT4 75 #define clr_GATE_T0 TMOD &= ~SET_BIT3 76 #define clr_CT_T0 TMOD &= ~SET_BIT2 77 #define clr_M1_T0 TMOD &= ~SET_BIT1 78 #define clr_M0_T0 TMOD &= ~SET_BIT0 79 80 //**** TH1 8AH **** 81 //**** TH0 8BH **** 82 //**** TL1 8CH **** 83 //**** TL0 8DH **** 84 85 //CKCON - 8EH 时钟控制寄存器 86 #define set_PWMCKS CKCON |= SET_BIT6 //设置pwm时钟源为定时器1的溢出(0为系统时钟，1为定时器1的溢出) 87 #define set_T1M CKCON |= SET_BIT4 //设置定时器1的时钟为系统时钟(0为1/12系统时钟,与8051兼容，1为选择时钟源为系统时钟) 88 #define set_T0M CKCON |= SET_BIT3 //设置定时器0的时钟为系统时钟(0为1/12系统时钟,与8051兼容，1为选择时钟源为系统时钟) 89 #define set_CLOEN CKCON |= SET_BIT1 //设置系统时钟输出使能,从PLO(P1.1)输出(0禁用系统时钟输出,1使系统时钟创覲LO(P1.1)输出) 90 //清除时钟 91 #define clr_PWMCKS CKCON &= ~SET_BIT6 //设置pwm时钟源为系统时钟(0为系统时钟，1为定时器1的溢出) 92 #define clr_T1M CKCON &= ~SET_BIT4 //设置定时器1的时钟为1/12系统时钟(0为1/12系统时钟,与8051兼容，1为选择时钟源为系统时钟) 93 #define clr_T0M CKCON &= ~SET_BIT3 //设置定时器0的时钟为1/12系统时钟(0为1/12系统时钟,与8051兼容，1为选择时钟源为系统时钟) 94 #define clr_CLOEN CKCON &= ~SET_BIT1 //设置系统时钟输出使能,禁用系统时钟输出(0禁用系统时钟输出,1使系统时钟创覲LO(P1.1)输出) 95 96 //**** WKCON 8FH **** 97 #define set_WKTCK WKCON |= SET_BIT5 98 #define set_WKTF WKCON |= SET_BIT4 99 #define set_WKTR WKCON |= SET_BIT3 100 #define set_WKPS2 WKCON |= SET_BIT2 101 #define set_WKPS1 WKCON |= SET_BIT1 102 #define set_WKPS0 WKCON |= SET_BIT0 103 104 #define clr_WKTCK WKCON &= ~SET_BIT5 105 #define clr_WKTF WKCON &= ~SET_BIT4 106 #define clr_WKTR WKCON &= ~SET_BIT3 107 #define clr_WKPS2 WKCON &= ~SET_BIT2 108 #define clr_WKPS1 WKCON &= ~SET_BIT1 109 #define clr_WKPS0 WKCON &= ~SET_BIT0 110 111 /**** P1 90H *****/ 112 #define set_P10 P10 = 1 113 #define set_P11 P11 = 1 114 #define set_P12 P12 = 1 115 #define set_P13 P13 = 1 116 #define set_P14 P14 = 1 117 #define set_P15 P15 = 1 118 #define set_P16 P16 = 1 119 #define set_P17 P17 = 1 120 121 #define clr_P10 P10
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