verilog之计数器0~9999——数码管显示

最新推荐文章于 2023-01-16 17:20:45 发布

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最新推荐文章于 2023-01-16 17:20:45 发布

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文章标签： c/c++

原文链接：http://www.cnblogs.com/CodeWorkerLiMing/archive/2012/06/07/2540850.html

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本文介绍了使用Verilog实现从0到9999计数，并在数码管上显示的示例代码。文章提到，Verilog语法相对简单，代码中包含多个并行执行的always语句。开发环境为DE0开发板与Quartus II 8.1 Web Edition。作者通过Tcl脚本完成了引脚分配和原理图文件的创建，最终实现了硬件下载与运行，展示了计数结果。

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verilog的语法是比较好理解的，当然是相对于VHDL楼，废话不说，直接上代码：

/*
file name     :     led4_cnt.v(for 4-bit)
author        :    LiMing
date        :    2012/06/07
description    :     Light one bit 7-segment and display 0 1 2 ... e f. in every constant time
fpga        :    Cyclone III    EP3C16F484C6
board        :    DE0 (ter-asic Ltd.)

successful!!! in DE0 board

unsigned char code[]=
{
    0x40, 0x79, 0x24, 
    0x30, 0x19, 0x12,
    0x02, 0x78, 0x00,
    0x10, 0x08, 0x03,
    0x46, 0x21, 0x06,
    0x0e       
};
*/

module led4_cnt(clk_50, sega7, segb7, segc7, segd7);
    
    input          clk_50;
    output [6:0] sega7;
    reg [6:0]      sega7;
    output [6:0] segb7;
    reg [6:0]      segb7;
    output [6:0] segc7;
    reg [6:0]      segc7;
    output [6:0] segd7;
    reg [6:0]      segd7;
    
    reg clk1k;    //frequency division //1khz 
    reg clk1hz;    //second clk signal
    
    reg [14:0]     count_1khz;    //count for frequency division 
    //reg [24:0]    count_1hz;    
    reg [8:0]    count_1hz;    
    
    reg [3:0]     num_ge;
    reg [3:0]    num_shi;
    reg [3:0]    num_bai;
    reg [3:0]    num_qian;
    
    parameter time_limited_1khz = 15'd25_000;
    //parameter time_limited_1hz = 25'd25_000_000;
    parameter time_limited_1hz = 9'd500;
    
    
    initial 
        begin
            sega7 <= 7'b100_0000;
            segb7 <= 7'b111_1001;
            segc7 <= 7'b010_0100;
            segd7 <= 7'b011_0000;
            num_ge = 4'd0;
            num_shi = 4'd0;
            num_bai = 4'd0;
            num_qian = 4'd0;
            clk1k = 1'd0;
            clk1hz = 1'd0;
        end
    
    //分频电时钟模块路 generate 1khz
    always@(posedge clk_50)//50M-1k,50M/1k/2//分频,50Mhz~1khz,占空比50% 
        begin 
            if(count_1khz == time_limited_1khz) 
                begin
                    clk1k <= ~clk1k; 
                    count_1khz <= 0; 
                end
            else