Last Major Update
Initial Release - December 16th 2010 – Cyclone III DDR2 SDRAM x32 167MHz, Quartus II v7.2, DDR2 SDRAM High Performance Controller, Cyclone III FPGA development kit.
Design Overview
This design is meant as a demo style lab. It very briefly covers the steps required to successfully get a DDR2 SDRAM interface working with a Cyclone III FPGA using DDR2 SDRAM component on the Cyclone III FPGA development kit. The purpose of the lab is for the reader to get a basic feel for what steps are involved in getting an external memory working with an Altera FPGA and the DDR2 High Performance Controller IP (ALTMEMPHY). The lab will not cover any of the steps in detail but simply show an overview of the design process. Volume 6 of the External Memory Interface Handbook should be used for a more thorough walkthrough.
The lab creates a 32bit 167MHz DDR2 SDRAM external memory PHY and controller using Altera’s DDR2 High Performance Controller IP (ALTMEMPHY). The IP also generates an example top level file, an example driver, and a test bench including an external memory model. All these will be used to demonstrate the DDR2 SDRAM functionality
Design Specifications
The table below lists the specifications for this design:
| Attribute | Specification |
| Quartus version | QuartusII v7.2 |
| FPGA | EP3C120F780C7 |
| Kit | Cyclone III FPGA development kit |
| Memory device | DDR2 SDRAM (Micron MT47H32M16CC-3) |
| Memory speed | 333MHz |
| Memory topology | Component, x32 |
| IP used | DDR2 High Performance Controller IP (ALTMEMPHY) and generated example top Quartus project |
Lab Steps
The lab uses Quartus II v7.2 and has Modelsim set up via NativeLink for simulation. The lab assumes the reader is a competent user of these tools and many of their features.
A Quartus archive for the final project is also included for reference.
Files for this lab are located in this zip file – CIII_DDR2_ALTMEMPHY.zip
Create a new folder for the project and place the files in it.
Design Generation
1. Use the Megawizard Plug-in Manager to generate a DDR2 SDRAM high-performance controller
Start Quartus, open MegaWizard Plug-In Manager and create a new variation
-
In the Megawizard GUI, set device family to be Cyclone III
-
The IP is located under the folders Interfaces/External Memory/DDR2 SDRAM, choose DDR2 SDRAM Controller with ALTMEMPHY
-
If your license for ModelSim can not support multiple HDL languages then chose verilog as output file type
-
For the name of the output file, browse to the folder you created above, give the instance the name “DDR2”, click Open, click Next to open the IP GUI
2. Set parameters for Memory Controller with ALTMEMPHY
-
Memory Settings Tab
- Set Speed Grade to 7
- Set Memory Clock Frequency to 166.667MHz
- Set PLL Reference Clock Frequency to 125MHz
- For the Memory Presets, select Micron MT47H32M16CC-3, which gives a 16-bit wide interface
- Change the memory interface DQ width to 32 in the memory preset editor
-
PHY Settings Tab
- Under Address/Command Clock Settings, for Dedicated clock phase type 90.
- Under Board Timing Parameters, for Board skew type 20 ps.
-
Click Next
-
Click Next
-
Turn the Generate simulation model option
-
Click “Finish” to start IP generation. Check important messages during generation. After IP is successfully generated, click Exit to close GUI
3. Set Top-Level Entity
The Megawizard generates a Quartus example top project. This project connects an example driver to the controller interface so users can quickly compile and test their ALTMEMPHY IP configuration on hardware.
-
Open the top-level entity file, <variation_name>_example_top.v or vhd
-
On the Project menu click Set as Top-Level Entity
4. Add Timing Constraints
To add timing constraints, perform the following steps:
-
On the Assignments menu click Settings.
-
In the Category list, expand Timing Analysis Settings, and select TimeQuest
-
Timing Analyzer.
-
Select the <variation_name>_phy_ddr_timing.sdc file and click Add.
-
Click OK.
5. Assign the pin and DQ group settings
Run the tcl script <variation_name>_pin_assignments.tcl to assign the pin and DQ group assignments. This tcl script is generated for you by the IP megawizard
-
Verify in the Assignment Editor that pin assignments have been created successfully
6. Assign the pin locations base on Cyclone III development board. Pin locations for external memory systems are not automatically created.
7. Do a Full Compile
Compile the example design.
Design Analysis
1. Timing Analysis results
-
In the Compilation Report, Time Quest Timing Analyzer folder expand the three VT model folders, and the Report DDR folder
- Check the summary at the bottom of that report
- Check that all setup and hold timings pass
Note: there will be some unconstrained paths in the design. These are associated with the example driver that will not be part of a fully integrated HP controller design.
2. On board debug with Signal Tap
Open the Signal Tap file and reset the .sof file to the one just created with the full compilation
-
Program the kit FPGA with the .sof
-
Run Signal Tap Analysis
- Restart the driver
- Ensure that test complete goes high (signal tap is trigger on this), this is the end of the driver testing, check the driver's pass signal is high.
Design Simulation
-
Run EDA RTL Simulation from Tools Menu – Run EDA Simulation Tool -> EDA RTL Simulation
- The simulation will stop once the test complete signal goes high in the test bench
- Observe the results in the ModelSim Wave window
Notes/Comments
Update History
1. Initial Release - December 16th 2010 - CIII DDR2 x32 167MHz, QuartusII v7.2, DDR2 SDRAM High Performance Controller, Cyclone III FPGA development kit.
See Also
1. List of designs using Altera External Memory IP
External Links
1. Altera's External Memory Interface Solutions Center
2. Altera's External Memory Interface Handbook
Key Words
ALTMEMPHY, HPCI, DDR2, Design Example, External Memory, Cyclone III, CIII
694
被折叠的 条评论
为什么被折叠?
到【灌水乐园】发言
