目录
EMIF接口与FPGA的互联(转)
通过EMIF接口控制各种芯片的复杂系统设计实现
DSP之外部设备连接接口之EMIF
TMS320C6455的EMIF与FPGA通讯
关于存储器按字节寻址和按字寻址的理解
Byte就是字节,1Byte = 8bit,
一个EMIF接口例程
`timescale 1ns/1ns
module emif_interface(
input clk,
input rst,
input emif_wr,
input emif_rd,
input [3:0] emif_ce,
input [23:0] emif_addr,
inout [15:0] emif_data, //inout parameter
output clk_out,
input [15:0] data_from_fpga_1,
input [15:0] data_from_fpga_2,
input [15:0] data_from_fpga_3,
input [15:0] data_from_fpga_4,
input rx_fifo_empty_1,
input rx_fifo_empty_3,
output reg wr_en_uart_1,
output reg [15:0] data_to_uart_1,
output reg wr_en_uart_2,
output reg [15:0] data_to_uart_2,
output reg wr_en_uart_3,
output reg [15:0] data_to_uart_3,
output reg wr_en_uart_4,
output reg [15:0] data_to_uart_4,
input [15:0] data_from_uart_1,
output reg rd_en_uart_1,
input [15:0] data_from_uart_2,
output reg rd_en_uart_2,
input [15:0] data_from_uart_3,
output reg rd_en_uart_3,
input [15:0] data_from_uart_4,
output reg rd_en_uart_4,
output [15:0] data_from_dsp_1,
output [15:0] data_from_dsp_2,
output [15:0] data_from_dsp_3,
output [15:0] data_from_dsp_4,
);
reg [3:0] emif_ce_dp0 = 4'b1111;
reg [3:0] emif_ce_dp1 = 4'b1111;
reg emif_ce1_dp2 = 1'b1;
reg emif_wr_dp0 = 1'b1;
reg emif_wr_dp1 = 1'b1;
reg emif_wr_dp2 = 1'b1;
reg emif_wr_dp3 = 1'b1;
reg emif_rd_dp0 = 1'b1;
reg emif_rd_dp1 = 1'b1;
reg rd_negedge;
reg wr_negedge;
reg [23:0] emif_addr_dp0;
reg [23:0] emif_addr_dp1;
reg [23:0] emif_addr_dp2;
reg [15:0] emif_data_dp0;
reg [15:0] emif_data_dp1;
reg [15:0] emif_data_dp2;
reg [15:0] data_from_fpga_1_d0;
reg [15:0] data_from_fpga_1_d1;
reg [15:0] data_from_fpga_2_d0;
reg [15:0] data_from_fpga_2_d1;
reg [15:0] data_from_fpga_3_d0;
reg [15:0] data_from_fpga_3_d1;
reg [15:0] data_from_fpga_4_d0;
reg [15:0] data_from_fpga_4_d1;
reg [15:0] data_from_dsp_1_d0;
reg [15:0] data_from_dsp_1_d1;
reg [15:0] data_from_dsp_2_d0;
reg [15:0] data_from_dsp_2_d1;
reg [15:0] data_from_dsp_3_d0;
reg [15:0] data_from_dsp_3_d1;
reg [15:0] data_from_dsp_4_d0;
reg [15:0] data_from_dsp_4_d1;
BUFG BUFG_inst
(
.O (clk_bufr),
.I (clk )
);
assign clk_out = clk_bufr;
always @(posedge clk_bufr)
if(rst)
begin
emif_ce_dp0 <= 4'b1111;
emif_ce_dp1 <= 4'b1111;
emif_ce1_dp2 <= 1'b1;
emif_wr_dp0 <= 1'b1;
emif_wr_dp1 <= 1'b1;
emif_wr_dp2 <= 1'b1;
emif_wr_dp3 <= 1'b1;
emif_rd_dp0 <= 1'b1;
emif_rd_dp1 <= 1'b1;
end
else
begin
emif_ce_dp0 <= emif_ce;
emif_ce_dp1 <= emif_ce_dp0;
emif_ce1_dp2 <= emif_ce_dp1[1];
emif_wr_dp0 <= emif_wr;
emif_wr_dp1 <= emif_wr_dp0;
emif_wr_dp2 <= emif_wr_dp1;
emif_wr_dp3 <= emif_wr_dp2;
emif_rd_dp0 <= emif_rd;
emif_rd_dp1 <= emif_rd_dp0;
end
always @(posedge clk_bufr)
if(rst)
begin
wr_negedge <= 1'b0;
rd_negedge <= 1'b0;
end
else
begin
wr_negedge <= (!emif_wr_dp2) & emif_wr_dp3;
rd_negedge <= (!emif_rd_dp2) & emif_rd_dp3;
end
always @(posedge clk_bufr)
if(rst)
begin
emif_addr_dp0 <= 24'b0;
emif_addr_dp1 <= 24'b0;
emif_addr_dp2 <= 24'b0;
emif_data_dp0 <= 16'b0;
emif_data_dp1 <= 16'b0;
emif_data_dp2 <= 16'b0;
end
else
begin
emif_addr_dp0 <= emif_addr;
emif_addr_dp1 <= emif_addr_dp0;
emif_addr_dp2 <= emif_addr_dp1;
emif_data_dp0 <= emif_data;
emif_data_dp1 <= emif_data_dp0;
emif_data_dp2 <= emif_data_dp1;
end
///******************************* DSP reads data from emif interface*****************************///
reg [15:0] data_to_dsp;
assign emif_data = emif_rd_dp1 ? 16'dz : (emif_ce_dp1[1] ? 16dz : data_to_dsp);
always @(posedge clk_bufr)
if(rst)
begin
data_from_fpga_1_d0 <= 16'd0;
data_from_fpga_1_d1 <= 16'd0;
data_from_fpga_2_d0 <= 16'd0;
data_from_fpga_2_d1 <= 16'd0;
data_from_fpga_3_d0 <= 16'd0;
data_from_fpga_3_d1 <= 16'd0;
data_from_fpga_4_d0 <= 16'd0;
data_from_fpga_4_d1 <= 16'd0;
end
else
begin
data_from_fpga_1_d0 <= data_from_fpga_1;
data_from_fpga_1_d1 <= data_from_fpga_1_d0;
data_from_fpga_2_d0 <= data_from_fpga_2;
data_from_fpga_2_d1 <= data_from_fpga_2_d0;
data_from_fpga_3_d0 <= data_from_fpga_3;
data_from_fpga_3_d1 <= data_from_fpga_3_d0;
data_from_fpga_4_d0 <= data_from_fpga_4;
data_from_fpga_4_d1 <= data_from_fpga_4_d0;
end
always @(posedge clk_bufr)
if(rst)
begin
data_to_dsp <= 16'd0;
end
else
begin
case(emif_ce_dp0[1],emif_addr_dp0[5:0])
7'b0_000001:
data_to_dsp <= data_from_uart_1;
7'b0_000010:
data_to_dsp <= data_from_uart_2;
7'b0_000011:
data_to_dsp <= data_from_uart_3;
7'b0_000100:
data_to_dsp <= data_from_uart_4;
7'b0_000101:
data_to_dsp <= data_from_fpga_1_d1;
7'b0_000110:
data_to_dsp <= data_from_fpga_2_d1;
7'b0_000111:
data_to_dsp <= data_from_fpga_3_d1;
7'b0_001000:
data_to_dsp <= data_from_fpga_4_d1;
default:
data_to_dsp <= data_to_dsp;
endcase
end
always @(posedge clk_bufr)
if(rst)
begin
rd_en_uart_1 <= 1'd0;
rd_en_uart_2 <= 1'd0;
rd_en_uart_3 <= 1'd0;
rd_en_uart_4 <= 1'd0;
end
else
begin
case(emif_ce_dp0[1],emif_addr_dp0[5:0])
7'b0_000001:
rd_en_uart_1 <= rd_negedge;
7'b0_000010:
rd_en_uart_2 <= rd_negedge;
7'b0_000011:
rd_en_uart_3 <= rd_negedge;
7'b0_000100:
rd_en_uart_4 <= rd_negedge;
default:
begin
rd_en_uart_1 <= 1'd0;
rd_en_uart_2 <= 1'd0;
rd_en_uart_3 <= 1'd0;
rd_en_uart_4 <= 1'd0;
end
endcase
end
///******************************* DSP writes data to emif interface*****************************///
always @(posedge clk_bufr)
if(rst)
begin
data_from_dsp_1_d1 <= 16'd0;
data_from_dsp_2_d1 <= 16'd0;
data_from_dsp_3_d1 <= 16'd0;
data_from_dsp_4_d1 <= 16'd0;
data_to_uart_1 <= 16'd0;
data_to_uart_2 <= 16'd0;
data_to_uart_3 <= 16'd0;
data_to_uart_4 <= 16'd0;
end
else if(!emif_wr_dp2)
begin
case(emif_ce1_dp2,emif_addr_dp2[5:0])
7'b0_001001:
data_from_dsp_1_d1 <= emif_data_dp2;
7'b0_001010:
data_from_dsp_2_d1 <= emif_data_dp2;
7'b0_001011:
data_from_dsp_3_d1 <= emif_data_dp2;
7'b0_001100:
data_from_dsp_4_d1 <= emif_data_dp2;
7'b0_001101:
data_to_uart_1 <= emif_data_dp2;
7'b0_001110:
data_to_uart_2 <= emif_data_dp2;
7'b0_001111:
data_to_uart_3 <= emif_data_dp2;
7'b0_010000:
data_to_uart_4 <= emif_data_dp2;
default:
begin
data_from_dsp_1_d1 <= data_from_dsp_1_d1;
data_from_dsp_2_d1 <= data_from_dsp_2_d1;
data_from_dsp_3_d1 <= data_from_dsp_3_d1;
data_from_dsp_4_d1 <= data_from_dsp_4_d1;
data_to_uart_1 <= 16'd0;
data_to_uart_2 <= 16'd0;
data_to_uart_3 <= 16'd0;
data_to_uart_4 <= 16'd0;
end
endcase
end
always @(posedge clk_bufr)
if(rst)
begin
wr_en_uart_1 <= 1'd0;
wr_en_uart_2 <= 1'd0;
wr_en_uart_3 <= 1'd0;
wr_en_uart_4 <= 1'd0;
end
else if(!emif_wr_dp2)
begin
case(emif_ce1_dp2,emif_addr_dp2[5:0])
7'b0_001101:
wr_en_uart_1 <= wr_negedge;
7'b0_001110:
wr_en_uart_2 <= wr_negedge;
7'b0_001111:
wr_en_uart_3 <= wr_negedge;
7'b0_001000:
wr_en_uart_4 <= wr_negedge;
default:
begin
wr_en_uart_1 <= 1'd0;
wr_en_uart_2 <= 1'd0;
wr_en_uart_3 <= 1'd0;
wr_en_uart_4 <= 1'd0;
end
endcase
end
always @(posedge clk_bufr)
if(rst)
begin
data_from_dsp_1_d0 <= 16'd0;
data_from_dsp_1 <= 16'd0;
data_from_dsp_2_d0 <= 16'd0;
data_from_dsp_2 <= 16'd0;
data_from_dsp_3_d0 <= 16'd0;
data_from_dsp_3 <= 16'd0;
data_from_dsp_4_d0 <= 16'd0;
data_from_dsp_4 <= 16'd0;
end
else
begin
data_from_dsp_1_d0 <= data_from_dsp_1_d1;
data_from_dsp_1 <= data_from_dsp_1_d0;
data_from_dsp_2_d0 <= data_from_dsp_2_d1;
data_from_dsp_2 <= data_from_dsp_2_d0;
data_from_dsp_3_d0 <= data_from_dsp_3_d1;
data_from_dsp_3 <= data_from_dsp_3_d0;
data_from_dsp_4_d0 <= data_from_dsp_4_d1;
data_from_dsp_4 <= data_from_dsp_4_d0;
end
ila_0 U_emif_interface
(
.clk (clk_bufr),
.probe0 (emif_addr_dp2[5:0],emif_ce1_dp2,data_to_dsp,emif_wr_dp2,rd_negedge,wr_negedge,emif_data_dp2)
);
endmodule