paper:synthesizable finite state machine design techniques using the new systemverilog 3.0 enhanceme...

1.the fsm coding style should be easily modifiable to change state encoding and FSM styles.

             FSM 的的 状态编码和风格易于改变

2.the coding style should be compact.

            代码比较紧凑

3.the coding style should facilitate debugging.

          代码易于debug

4.the coding style should yield efficient synthesis results.

          基于综合做coding

 

Important common guidelines :

   Guideline:Make each FSM design a separate Verilog moulde.

           一个module中只有一个FSM 。

 Guideline:Use parameters to define state encoding instead of the Verilog `define macro definition construct.

    能用parameter 就不用define ,当定义状态编码时。

 Guideline:When creating verilog constants,think parameters first,then find good justification before changing to use a global `define macro.

    如果真的需要全局常量就用define,否则尽量用parameter,当定义一个常量时。

  most verilog constants should be coded using parameters.

 

 

parameter 定义的是模块局部的，define 定义的是全局的，整个project都可以看到。

Guideline: make state and next(next state) declarations right before the parameter assignments

       先声明后使用。

Guideline：Code all sequential always block using nonblocking assignments(<=).

Guideline : Code al combinational always block using blocking assignments(=).

    防止race conditions

转载于:https://www.cnblogs.com/chip/p/5468039.html