SystemVerilog for Design（Chapter2）--SystemVerilog Declaration Spaces

SystemVerilog for Design（Chapter2）–SystemVerilog Declaration Spaces

Topic:

• Packages definitions and importing definitions from packages

• $unit compilation declaration space

• Declarations in unnamed blocks

• Enhanced time unit definitions

1. Packages definitions and importing definitions from packages

1.1 Package definitions

SystemVerilog adds usr-defined types , using typedef. To enable sharing a usr-defined type definition accross multiple modules , SystemVerilog adds package to the Verilog language, defined between the keywords package and ** endpackage**.

A package which is synthesizable one can contain:

• parameter and localparam constant definitions
• const variable definitions
• typedef usr-define types
• fully automatic task and function definitions
• import statement from other packages.
• Operator overload definitions
  Package can also contain global variable declarations, static task and static function definitions. we won’t discuss these in this blog.

Package definitions are independent of modules. A simple example of a package definition is :

package definitions;
	parameter VERSION = "1.1";
	typedef enum {
   ADD,SUB,MUL} opcodes_t;
	typedef struct{
   
		logic [31:0] a,b;
		opcodes_t opcode;
	} instruction_t;
	function automatic [31:0] multiplier (input [31:0] a, b);
		//code for a custom 32bit multiplier goes here;
		return a*b;//abstract multiplier (no error detection)
	endfunction
endpackage

In a package,a parameter constant can not be redefined, since it is not part of a module instance. In a package, parameter and localparam are synonymous.

1.2 Referencing Package Contents

Package references using the scope resolution operator, SystemVerilog adds a :: “scope resolution operator” to Verilog.

Example 2-2: Explicit package references using the :: scope resolution operator

module ALU(
	input definitions::instruction_t IW,
	input logic clock,
	output logic [31:0] result
);
	always_ff @(posedge clock) begin
		case (IW.opcode)
			definitions::ADD : result = IW.a + IW.b;
			definitions::SUB : result = IW.a - IW.b;
			definitions::MUL : result = definitions::multiplier(IW.a, IW.b);
		endcase
	end
endmodule

SystemVerilog allows specific package items to be imported into a module, using an import statement.

Example 2-3: Importing specific package items into a module

module ALU(
	input definitions::instruction_t IW,
	input logic clock,
	output logic [31:0] result
);
	import definitions::ADD;
	import definitions::SUB;
	import definitions::MUL;
	import definitions::multiplier;
	always_comb begin
		case (IW.opcode)
			ADD : result = IW.a + IW.b;
			SUB : result = IW.a - IW.b;
			MUL : result = multiplier(IW.a, IW.b);
		endcase
	end
endmodule

NOTE-> Importing an enumerated type definition does not import the labels used within that definition.
"import definitions::opcode_t;" wouldn’t work.

Wildcard import of package items

A