modelsim do文件仿真

1.编写sim.do文件

##### Quit the Simulation #####

quit -sim

 

##### Make work directory &&　Create the Project/Lib #####

if {[file exists work]} {

file delete -force

work vlib work

puts "Successfully Created work1 directory"

} else {

vlib work

puts "Successfully Created work directory"

}

 

##### Compile the verilog #####

vlog ../testbench/counter_tb.v

vlog ../prj/ip/counter.v

 

##### Start Simulation #####

vsim -t ps -novopt -L lpm -L altera_mf -L altera_primitives work.counter_tb

radix hex

add wave -position insertpoint sim:/counter_tb/counter0/*

run -all

2.modelsim_run.bat文件

modelsim -do sim.do

转载于:https://www.cnblogs.com/billyzh/p/5627854.html