c语言安卓指令集,C语言和汇编Arm64 指令集the_a64_Instruction_set_100898_0100

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1、The A64 instruction set Copyright 2017 ARM Limited or its affiliates. All rights reserved. Page 1 of 35 ARM 100898_0100_en Connect User Guide Version 0.1 ARM DD1ID113009 The A64 instruction set Version 1.0 The A64 instruction set Copyright 2017 ARM Limited or its affiliates. All rights reserved. Pag。

2、e 2 of 35 ARM 100898_0100_en Revision Information The following revisions have been made to this User Guide. Date Issue Confidentiality Change 03 March 2017 0100 Non-Confidential First release Proprietary Notice Words and logos marked with or are registered trademarks or trademarks of ARM in the EU 。

3、and other countries, except as otherwise stated below in this proprietary notice. Other brands and names mentioned herein may be the trademarks of their respective owners. Neither the whole nor any part of the information contained in, or the product described in, this document may be adapted or rep。

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5、 all warranties implied or expressed, including but not limited to implied warranties of merchantability, or fitness for purpose, are excluded. This document is intended only to assist the reader in the use of the product. ARM shall not be liable for any loss or damage arising from the use of any in。

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7、may be subject to license restrictions in accordance with the terms of the agreement entered into by ARM and the party that ARM delivered this document to. Unrestricted Access is an ARM internal classification. Product Status The information in this document is final, that is for a developed product。

8、. Web Address The A64 instruction set Copyright 2017 ARM Limited or its affiliates. All rights reserved. Page 3 of 35 ARM 100898_0100_en Contents 1 The A64 instruction set . 5 1.1 Instruction mnemonics . 5 Distinguishing between 32-bit and 64-bit A64 instructions. 5 2 Data processing instructions . 。

9、7 2.1 Arithmetic and logical operations . 7 2.2 Multiply instructions . 9 2.3 Divide instructions . 10 2.4 Shift operations . 11 2.5 Shift operators . 11 2.6 Byte and bitfield manipulation instructions . 13 Extend operators . 15 2.7 Conditional instructions . 17 Conditional operations . 18 Condition。

10、al select (move) . 18 Conditional set . 19 Conditional compare . 19 3 Memory access instructions . 20 3.1 Load instruction format . 20 3.2 Store instruction format . 21 3.3 SIMD (NEON) and floating-point scalar loads and stores . 21 3.4 Specifying the address for a Load or Store instruction . 22 Off。

11、set modes . 23 Index modes . 23 3.5 Literal pools . 24 PC-relative loads . 25 3.6 Accessing multiple memory locations . 25 3.7 Unprivileged access . 26 3.8 Prefetching memory . 26 3.9 Non-temporal load and store pair . 27 3.10 Memory access atomicity . 27 3.11 Memory barrier instructions . 27 3.12 S。

12、ynchronization primitives . 28 4 Flow control . 29 The A64 instruction set Copyright 2017 ARM Limited or its affiliates. All rights reserved. Page 4 of 35 ARM 100898_0100_en 5 System control and other instructions. 31 5.1 Exception generating instructions . 31 5.2 Exception return instructions . 31 。

13、From AArch64 state . 31 5.3 System register access . 31 5.4 Debug instructions . 32 5.5 Hint instructions . 32 5.6 SIMD instructions . 33 5.7 Floating-point instructions . 33 5.8 Cryptographic instructions . 34 The A64 instruction set Copyright 2017 ARM Limited or its affiliates. All rights reserved。

14、. Page 5 of 35 ARM 100898_0100_en 1 The A64 instruction set One of the most significant changes introduced in the ARMv8-A architecture was the addition of an instruction set for AArch64, called A64. This instruction set contains features similar to the existing AArch32 (ARMv7-A) 32-bit instruction s。

15、et. The addition of A64 provides access to 64-bit wide integer registers and data operations, and the ability to use 64-bit sized pointers to memory. The A64 instructions execute in the AArch64 Execution state. ARMv8-A also includes the original ARM instruction set, now called A32, and the Thumb (T3。

16、2) instruction set. Programmers writing at the application level might never need to write code in assembly language. However, assembly code can be useful in cases when highly optimized code is required. This is the case when writing compilers, or where using low level features not directly availabl。

17、e in C is required, for example: Portions of boot code. Device drivers. Operating system development. Reading assembly code can be helpful for debugging C, particularly to understand the mapping between assembly instructions and C statements. 1.1 Instruction mnemonics The A64 instruction set overloa。

18、ds instruction mnemonics. That is, it distinguishes between the different forms of an instruction, based on the operand register names that are used. For example, the following ADD instructions all have different forms, but you only have to remember one instruction and the assembler automatically ch。

19、ooses the correct encoding, based on the operands used. ADD W0, W1, W2 / add 32-bit registers ADD X0, X1, X2 / add 64-bit registers ADD X0, X1, W2, SXTW / add sign extended 32-bit register to 64-bit / extended register ADD X0, X1, #42 / add immediate to 64-bit register ADD V0.8H, V1.8H, V2.8H / NEON。

20、 16-bit add, in each of 8 lanes Distinguishing between 32-bit and 64-bit A64 instructions Most integer instructions in the A64 instruction set have two forms, which operate on either 32- bit or 64-bit values within the 64-bit general-purpose register file. When looking at the register name that the 。

21、instruction uses: If the register name starts with X, it is a 64-bit register. If the register name starts with W, it is a 32-bit register. The A64 instruction set Copyright 2017 ARM Limited or its affiliates. All rights reserved. Page 6 of 35 ARM 100898_0100_en When a 32-bit register form is select。

22、ed: Right shifts and rotates inject at bit 31, instead of bit 63. The condition flags, where set by the instruction, are computed from the lower 32 bits. Writes to the W register set bits 63:32 of the X register to zero. This distinction applies even when the results of a 32-bit register form would 。

23、be indistinguishable from the lower 32 bits computed by the equivalent 64-bit register form. For example, A64 includes separate 32-bit and 64-bit register forms of the ORR instructions. A 32-bit bitwise ORR could just as easily be performed using a 64-bit ORR and ignoring the top 32 bits of the resu。

24、lt. The A64 instruction set Copyright 2017 ARM Limited or its affiliates. All rights reserved. Page 7 of 35 ARM 100898_0100_en 2 Data processing instructions These are the fundamental arithmetic and logical operations of the processor and operate on values in general-purpose registers, or on a regis。

25、ter and an immediate value. A64 deals naturally with 64-bit signed and unsigned data types by offering more concise and efficient ways of manipulating 64-bit integers. This can be advantageous for all languages that provide 64-bit integers such as C or Java. Multiply instructions can be considered s。

26、pecial cases of these instructions. Data processing instructions mostly use one destination register and two source operands. The general format can be considered as the instruction, followed by the operands, as follows: Instruction Rd, Rn, Operand2 Where Rd is the destination register. Rn is the re。

27、gister that is operated on. The use of R here indicates that the registers can be either X or W registers. Operand2 might be a register, a modified register, or an immediate value. Data processing operations include: Arithmetic and logical operations. Move and shift operations. Instructions for sign。

28、 and zero extension. Bit and bitfield manipulation. Conditional comparison and data processing. 2.1 Arithmetic and logical operations Some of the available operations are shown in the following table. Type Instructions Arithmetic ADD, SUB, ADC, SBC, NEG Logical AND, BIC, ORR, ORN, EOR, EON Compariso。

29、n CMP, CMN, TST Move MOV, MVN Some of these instructions also have an S suffix, indicating that the instruction sets flags. Of the above instructions, those taking the suffix include ADDS, SUBS, ADCS, SBCS, ANDS, and BICS. There are other flag setting instructions, notably CMP, CMN, and TST, but the。

30、se do not take an S suffix. The A64 instruction set Copyright 2017 ARM Limited or its affiliates. All rights reserved. Page 8 of 35 ARM 100898_0100_en The operations ADC and SBC perform additions and subtractions that also use the carry condition flag as an input. ADCS: Rd = Rn + Rm + C SBCS: Rd = R。

31、n - Rm - 1 + C For example: Loop ADD W0, W1, W2, LSL #3 / W0 = W1 + (W2 2), set flags BGE Loop / Loop if not negative MOV X0, X1 / Copy X1 to X0 CMP W3, W4 / Set flags based on W3 - W4 ADD W0, W5, #27 / W0 = W5 + 27 The logical operations are the same as the corresponding Boolean operators operating。

32、 on individual bits of the register. For example: AND X2, X2, X1 ORR W2, W2, W5 EOR W7, W7, W6 BIC X0, X0, X1 The BIC (Bitwise bit Clear) instruction (BIC Rd, Rn, Operand2): Inverts Operand2. Performs a bitwise AND with Rn. Stores the result in Rd. For example, to clear bit 11 of register X0, use: M。

33、OV X1, #0 x800 BIC X0, X0, X1 ORN Rd, Rn, Operand2 inverts Operand2 and ORs with Rd. EON Rd, Rn, Operand2 inverts Operand2 and EORs with Rd. The comparison instructions only modify the flags and have no other effect. The range of immediate values for these instructions is 12 bits, and the immediate 。

34、value can be shifted 12 bits to the left. The A64 instruction set Copyright 2017 ARM Limited or its affiliates. All rights reserved. Page 9 of 35 ARM 100898_0100_en 2.2 Multiply instructions The multiply instructions that are provided are broadly similar to those in ARMv7-A, but have the ability to 。

35、perform 64-bit multiplies in a single instruction. Instruction Description MADD Multiply add MNEG Multiply negate MSUB Multiply subtract MUL Multiply SMADDL Signed multiply-add long SMNEGL Signed multiply-negate long SMSUBL Signed multiply subtract long SMULH Signed multiply returning high half SMUL。

36、L Signed multiply long UMADDL Unsigned multiply-add long UMNEGL Unsigned multiply-negate long UMSUBL Unsigned multiply subtract long UMULH Unsigned multiply returning high half UMULL Unsigned multiply long There are multiply instructions that operate on 32-bit or 64-bit values and return a result of。

37、 the same size as the operands. For example, two 64-bit registers can be multiplied to produce a 64-bit result with the MUL instruction. Any overflow is ignored and the result is taken as the lower 64 bits. MUL X0, X1, X2 / X0 = X1 X2 There is also the ability to add or subtract an accumulator value。

38、 in a third source register, using the MADD or MSUB instructions. The MNEG instruction can be used to negate the result, for example: MNEG X0, X1, X2 / X0 = -(X1 X2) Also, there are a range of multiply instructions that produce a long result, that is, multiplying two 32-bit numbers and generating a 。

39、64-bit result. There are both signed and unsigned variants of these long multiplies (UMULL, SMULL). There are also options to accumulate a value from another register (UMADDL, SMADDL) or to negate (UMNEGL, SMNEGL). Including 32-bit and 64-bit multiply with optional accumulation gives a result size t。

40、hat is the same size as the operands. Again, any overflow is ignored and the result is taken as the lower 64 bits of the calculation: 32 (32 32) gives a 32-bit result. The A64 instruction set Copyright 2017 ARM Limited or its affiliates. All rights reserved. Page 10 of 35 ARM 100898_0100_en 64 (64 6。

41、4) gives a 64-bit result. (32 32) gives a 32-bit result. (64 64) gives a 64-bit result. Both signed and unsigned widening multiply with accumulation give a single 64-bit result: 64 (32 32) gives a 64-bit result. (32 32) gives a 64-bit result. A 64 64 to 128-bit multiplication has the potential to ge。

42、nerate a result that is larger than 64 bits. This causes the result register of the standard MUL instruction to overflow. In this case, the signed/unsigned multiply high instructions (SMULH, UMULH) captures the bits of the result lost by the overflow in another register. For example, the operation 0。

43、 xFFFF_FFFF_FFFF_FFFF x 0 x2 would give the answer 0 x1_FFFF_FFFF_FFFF_FFFE which will not fit into a single 64 bit register. MOV X0, #0 xFFFFFFFFFFFFFFFF MOV X1, #0 x2 MUL X2, X0, X1 / X2 = 0 xFFFF_FFFF_FFFF_FFFE UMULH X3, X0, X1 / X3 = 0 x0000_0000_0000_0001 Note You cannot directly multiply a 32-。

44、bit W register by a 64-bit X register. 2.3 Divide instructions ARMv8-A supports signed and unsigned division of 32-bit and 64-bit sized values. Instruction Description SDIV Signed divide UDIV Unsigned divide For example: UDIV W0, W1, W2 / W0 = W1 / W2 (unsigned, 32-bit divide) SDIV X0, X1, X2 / X0 =。

45、 X1 / X2 (signed, 64-bit divide) Overflow and divide-by-zero are not trapped: Any integer division by zero returns zero. Overflow can only occur in SDIV: o INT_MIN / -1 returns INT_MIN, where INT_MIN is the smallest negative number that can be encoded in the registers that are used for the operation。

46、. The result is always rounded towards zero, as in most C/C+ dialects. The A64 instruction set Copyright 2017 ARM Limited or its affiliates. All rights reserved. Page 11 of 35 ARM 100898_0100_en 2.4 Shift operations The following instructions move the bit patterns within a register to the left or to the right: Logical Shift Left (LSL). The LSL instruction performs multiplication by a power of 2. Logical Shift Right (LSR). The。