FPGA 之 VGA的IP核编写

做一个简单的VGA 640*480   超了一天半， 整整七天才搞定，不过也很开心了！  加油努力.....

 

主要分成三个文件: 

VGA.v 主文件, 同时调用FIFO

vga_timing.v VGA时序控制文件

vga_sdram.v 读取SDRAM内存文件

 

 

 

1. VGA.v 

 

module VGA(
input wire clk,
input wire reset,

// 控制寄存器读写
input wire slave_chipselect,
input wire[1:0] slave_address, //
input wire slave_write, //写请求
input wire[31:0] slave_writedata, //写数据
input wire slave_read, //读请求
output wire[31:0] slave_readdata, //读数据
input wire[3:0] slave_byteenable, //数据有效标志

// 读写SDRAM数据
output wire[31:0] master_address, //数据地址
output wire master_read, //主端口读请求
output wire master_byteenable,
input wire master_waitrequest, //迫使主端口等待
input wire master_readdatavalid, //指示已经提供有效数据
input wire[7:0] master_readdata, //读入数据值

// VGA 时序
input wire vga_clk,
output wire vga_line_sync,
output wire vga_field_sync,
output wire [2:0] vga_r,
output wire [2:0] vga_g,
output wire [1:0] vga_b
);

wire vga_pixel_flag;

wire [7:0] fifo_data;
wire [7:0] tmp_data0;
reg [7:0] tmp_data1;

wire vga_frame_o;

 

/
// VGA输出 /
/

assign vga_b = vga_pixel_flag ? fifo_data[1:0]:8'b00000000;
assign vga_g = vga_pixel_flag ? fifo_data[4:2]:8'b00000000;
assign vga_r = vga_pixel_flag ? fifo_data[7:5]:8'b00000000;

/
// VGA 时序 /
/
vga_timing vga_l1(
.clk(vga_clk),
.reset_i(reset),
.pixel_flag(vga_pixel_flag),
.hsync(vga_line_sync),
.vsync(vga_field_sync),
.frame_o(vga_frame_o),
.vga_rgb(tmp_data0)
);

 

/
// VGA 寄存器操作 /
/

//register 操作寄存器
wire vga_go; //VGA 启动标志
wire [31:0] vga_base_address; //vga 数据基地址

vga_register vga_slave(
.clk(clk),
.reset_n(reset),

// 控制寄存器读写
.slave_chipselect(slave_chipselect),
.slave_address(slave_address), //
.slave_write(slave_write), //写请求
.slave_writedata(slave_writedata), //写数据
.slave_read(slave_read), //读请求
.slave_readdata(slave_readdata), //读数据
.slave_byteenable(slave_byteenable), //数据有效标志

.vga_base_address(vga_base_address),
.vga_go(vga_go)
);

 

/
// VGA SDRAM 读取像素 /
/

 

 

 

 

wire [11:0] fifo_count;

vga_sdram vga_sdram_11(
.clk(clk),
.reset_n(reset),

.master_address(master_address), //数据地址
.master_read(master_read), //主端口读请求
.master_byteenable(master_byteenable),
.master_waitrequest(master_waitrequest), //迫使主端口等待
.master_readdatavalid(master_readdatavalid),//指示已经提供有效数据
.master_readdata(master_readdata), //读入数据值

.vga_base_addr(vga_base_address), //VGA基地址
.vga_go(vga_go), //VGA 启动标记
.frame_start_flag(vga_frame_o), //帧开始标记
.fifo_count(fifo_count)
);

 

 

 

/
// VGA FIFO 做数据缓冲 以匹配不同速度的外设//
/

 

vga_fifo fifo_l2(
.aclr(vga_frame_o),
.data(master_readdata),
// .data(8'b00001000),
.rdclk(~vga_clk),
.rdreq(vga_pixel_flag),
.wrclk(clk),
.wrreq(master_readdatavalid),
.q(fifo_data),
.wrusedw(fifo_count)
);

 

 

endmodule

 

2. vga_timing.v 

 

 

//640*480
module vga_timing( clk,reset_i,pixel_flag,
hsync,
vsync,
frame_o,
vga_rgb);

// VGA

input clk;
input reset_i;
output hsync; //VGA行同步信号
output vsync; //VGA场同步信号
output pixel_flag;
output frame_o;
output[7:0] vga_rgb;

reg [10:0] hcount; //VGA行扫描计数器
reg [9:0] vcount; //VGA场扫描计数器
reg [8:0] data; //VGA数据
reg vga_clk;

wire h_end;
wire v_end;

wire dat_act;

 

// VGA

always @(posedge clk)
begin
vga_clk = ~vga_clk;
end
// 竖向....
always @(posedge clk)
begin
if(h_end)
hcount <= 10'd0;
else
hcount <= hcount + 10'd1;
end

assign h_end = (hcount == 799);

// 横向....
always @(posedge clk)
begin
if(h_end)
begin
if(v_end)
vcount <= 10'd0;
else
vcount <= vcount + 10'd1;
end
end
assign v_end = (vcount == 524);

//使能信号
assign pixel_flag = ((hcount >= 144) && (hcount < 784))&& ((vcount >= 34) && (vcount < 514));

 

assign hsync = (hcount > 95);//水平同步
assign vsync = (vcount > 2);//垂直同步

 

reg frame_o_t;
always @(posedge clk)
begin
if( vcount < 3)
frame_o_t <= 1;
else
frame_o_t <= 0;
end

assign frame_o = frame_o_t;//垂直同步

wire[10:0] x_pos;
wire[10:0] y_pos;
assign x_pos = hcount - 144;//垂直同步
assign y_pos = vcount - 34;//垂直同步

reg[7:0] vga_rgb_t;

always @(posedge clk)
begin

if( x_pos<500 && y_pos > 80)
vga_rgb_t <= 8'b01101111;
else
vga_rgb_t <= 8'b00000000;
end

assign vga_rgb = vga_rgb_t;

endmodule

 

 

3. vga_sdram.v

 

 

module vga_sdram(input wire clk,
input wire reset_n,

output wire[31:0] master_address, //数据地址
output wire master_read, //主端口读请求
output wire master_byteenable,
input wire master_waitrequest, //迫使主端口等待
input wire master_readdatavalid, //指示已经提供有效数据
input wire[7:0] master_readdata, //读入数据值

input wire[31:0] vga_base_addr, //VGA基地址
input wire vga_go, //VGA 启动标记
input wire frame_start_flag, //帧开始标记
input wire[11:0] fifo_count
);

 

reg [19:0] input_data_count;
reg vga_read;

assign master_read = vga_read;
assign master_byteenable = 1'd1; //位使能
assign master_address = vga_base_addr + input_data_count;

//统计FIFO已经读了多少数据
always @ (posedge clk or negedge reset_n)
begin
if (!reset_n)
begin
//vga_read <= 1'b0; //SDRAM 停止读
end

// 一帧数据开始时，清除FIFO
else if (!master_waitrequest ) //地址计数 : // 1. 数据有效
begin

if (frame_start_flag)
begin
vga_read <= 1'b0;
end
else if( (fifo_count < 500) && (input_data_count < 307200) )
begin
vga_read <= 1'b1; // 向FIFO读数据
end
else if(fifo_count > 2000)
begin
vga_read <= 1'b0; // 向FIFO读数据
end

end

end

always @ (posedge clk or negedge reset_n)
begin
if (!reset_n)
begin
//input_data_count <= 0;
end

// 一帧数据开始时，清除FIFO
else if (!master_waitrequest ) //地址计数 : // 1. 数据有效
begin

if (frame_start_flag)
begin
input_data_count <= 0;
end
else if( input_data_count < 307200)
begin
if(vga_read == 1'b1)
input_data_count <= input_data_count + 1;
end

end

end

 

endmodule

 

 

 

 

 

转载于:https://www.cnblogs.com/signal/archive/2012/07/31/2616745.html