FPGA中顶层模块与各子模块之间的连接线类型

顶层模块：mix_module

module mix_module
(
CLK, RSTn, Flash_LED, Run_LED
);

input CLK;
input RSTn;
output Flash_LED;
output [2:0]Run_LED;

/**********************************/

//wire Flash_LED;
//reg Flash_LED;

flash_module U1
(
.CLK( CLK ),
.RSTn( RSTn ),
.LED_Out( Flash_LED )
);

/**********************************/

//wire [2:0]Run_LED;
//reg [2:0]Run_LED;

run_module U2
(
.CLK( CLK ),
.RSTn( RSTn ),
.LED_Out( Run_LED )
);

/***********************************/

//assign Flash_LED = Flash_LED;
// assign Run_LED