数字跑表的verilog实现

数字跑表的verilog实现，用rst_n复位后开始计时，用pause暂停，输出为分、秒、百分秒的BCD码。

  1 module stop_watch(rst_n,
  2                         clk,
  3                         //start,
  4                         pause,
  5                         msl,
  6                         msh,
  7                         sl,
  8                         sh,
  9                         ml,
 10                         mh
 11                         );                                                
 12 input rst_n;
 13 input clk;
 14 //input start;
 15 input pause;
 16 output [3:0] msl;
 17 output [3:0] msh;
 18 output [3:0] sl;
 19 output [3:0] sh;
 20 output [3:0] ml;
 21 output [3:0] mh;
 22 
 23 reg [3:0] msl;
 24 reg [3:0] msh;
 25 reg [3:0] sl;
 26 reg [3:0] sh;
 27 reg [3:0] ml;
 28 reg [3:0] mh;
 29 
 30 reg msh_en;
 31 reg sl_en;
 32 reg sh_en;
 33 reg ml_en;
 34 reg mh_en;
 35 
 36 //update the 1/100 second low number
 37 //generate enable signal of 1/100 second high number
 38 always@(posedge clk or rst_n)
 39     if(!rst_n)
 40