利用74ls161设计bcd5421码十进制计数_用verilog HDL设计一个电子时钟（问题16）

Problem sixteen count clock—设计一个时钟

• 题干

Create a set of counters suitable for use as a 12-hour clock (with am/pm indicator). Your counters are clocked by a fast-running clk, with a pulse on ena whenever your clock should increment (i.e., once per second).

reset resets the clock to 12:00 AM. pm is 0 for AM and 1 for PM. hh, mm, and ss are two BCD (Binary-Coded Decimal) digits each for hours (01-12), minutes (00-59), and seconds (00-59). Reset has higher priority than enable, and can occur even when not enabled.

The following timing diagram shows the rollover behaviour from 11:59:59 AM to 12:00:00 PM and the synchronous reset and enable behaviour.

1. pm： 确定电子时钟的时区，输入0代表上午am，输入1代表下午pm
2. hh, mm, ss： 三者都是两个BCD数字，分别代表小时（01-12），分钟（00-59），秒（00-59）
3. ena：该信号为高时，电子时钟才能正常工作，与上题区别是，该信号是整