fpga map测试_test.map.rpt

最新推荐文章于 2022-03-24 00:27:00 发布

KellyWeaver

最新推荐文章于 2022-03-24 00:27:00 发布

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文章标签： fpga map测试

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; OUTDATA_ACLR_A ; NONE ; Untyped ;; WRCONTROL_ACLR_A ; NONE ; Untyped ;; INDATA_ACLR_A ; NONE ; Untyped ;; BYTEENA_ACLR_A ; NONE ; Untyped ;; WIDTH_B ; 8 ; Integer ;; WIDTHAD_B ; 6 ; Integer ;; NUMWORDS_B ; 64 ; Integer ;; INDATA_REG_B ; CLOCK1 ; Untyped ;; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ;; RDCONTROL_REG_B ; CLOCK1 ; Untyped ;; ADDRESS_REG_B ; CLOCK1 ; Untyped ;; OUTDATA_REG_B ; UNREGISTERED ; Untyped ;; BYTEENA_REG_B ; CLOCK1 ; Untyped ;; INDATA_ACLR_B ; NONE ; Untyped ;; WRCONTROL_ACLR_B ; NONE ; Untyped ;; ADDRESS_ACLR_B ; NONE ; Untyped ;; OUTDATA_ACLR_B ; NONE ; Untyped ;; RDCONTROL_ACLR_B ; NONE ; Untyped ;; BYTEENA_ACLR_B ; NONE ; Untyped ;; WIDTH_BYTEENA_A ; 1 ; Integer ;; WIDTH_BYTEENA_B ; 1 ; Untyped ;; RAM_BLOCK_TYPE ; AUTO ; Untyped ;; BYTE_SIZE ; 8 ; Untyped ;; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; Untyped ;; INIT_FILE ; UNUSED ; Untyped ;; INIT_FILE_LAYOUT ; PORT_A ; Untyped ;; MAXIMUM_DEPTH ; 0 ; Untyped ;; CLOCK_ENABLE_INPUT_A ; NORMAL ; Untyped ;; CLOCK_ENABLE_INPUT_B ; NORMAL ; Untyped ;; CLOCK_ENABLE_OUTPUT_A ; NORMAL ; Untyped ;; CLOCK_ENABLE_OUTPUT_B ; NORMAL ; Untyped ;; DEVICE_FAMILY ; Cyclone ; Untyped ;; CBXI_PARAMETER ; altsyncram_jam1 ; Untyped ;+------------------------------------+-----------------+--------------------------------------------+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "