背景：MTCNN的卷积被实现为IPcore
目的：HLS通过IPcore，输出RTL
目录
一、删掉一些语句
因bug找不出，只能暂且去掉一些优化指令。
225 删掉 DATAFLOW
240 删掉 UNROLL factor=N_PE
发现依然有报错，问题可能没出在这两点上。
WARNING: [XFORM 203-631] Renaming function 'ProcessingElement::processInputChannel.0' to 'processInputChannel.' (src/fpgaAcc.cpp:207:43)
WARNING: [XFORM 203-631] Renaming function 'ProcessingElement::processAll_channelOut' to 'processAll_channelOu' (src/fpgaAcc.cpp:192:50)
INFO: [XFORM 203-811] Inferring bus burst read of variable length on port 'memorybus' (src/fpgaAcc.cpp:178:15).
Instruction does not dominate all uses!
%tmp_64 = add i32 %WeightsCache_inChan_1, %tmp_63
%memorybus_addr_rd_re = call i1 @_ssdm_op_ReadReq.m_axi.floatP(float* %memorybus_addr, i32 %tmp_64), !dbg !1031
Broken module found, compilation aborted!
Stack dump:
0. Running pass 'Function Pass Manager' on module '/home/osrc/Desktop/document/conv_Core/HLS_Conv/conv3x3_IPcore/solution1/.autopilot/db/a.o.2.bc'.
1. Running pass 'Module Verifier' on function '@convolution_3x3'
/mnt/workspace/Xilinx/Vivado/2017.4/bin/loader: line 194: 47464 Aborted (core dumped) "$RDI_PROG" "$@"
Finished C synthesis.175,176 删掉 load_weight_2_reg 中 INLINE ,PIPELINE
synthesis通过了，但是时钟周期标红。
Starting C synthesis ...
/mnt/workspace/Xilinx/Vivado/2017.4/bin/vivado_hls /home/osrc/Desktop/document/conv_Core/HLS_Conv/conv3x3_IPcore/solution1/csynth.tcl
INFO: [HLS 200-10] Running '/mnt/workspace/Xilinx/Vivado/2017.4/bin/unwrapped/lnx64.o/vivado_hls'
INFO: [HLS 200-10] For user 'osrc' on host 'osrc-virtual-machine' (Linux_x86_64 version 4.13.0-32-generic) on Wed Dec 12 19:20:13 CST 2018
INFO: [HLS 200-10] On os Ubuntu 16.04.3 LTS
INFO: [HLS 200-10] In directory '/home/osrc/Desktop/document/conv_Core/HLS_Conv'
INFO: [HLS 200-10] Opening project '/home/osrc/Desktop/document/conv_Core/HLS_Conv/conv3x3_IPcore'.
INFO: [HLS 200-10] Adding design file 'src/fpgaAcc.cpp' to the project
INFO: [HLS 200-10] Adding design file 'src/fpgaAcc.hpp' to the project
INFO: [HLS 200-10] Adding design file 'src/pBox.cpp' to the project
INFO: [HLS 200-10] Adding design file 'src/pBox.h' to the project
INFO: [HLS 200-10] Adding test bench file 'src/test_convBench.cpp' to the project
INFO: [HLS 200-10] Opening solution '/home/osrc/Desktop/document/conv_Core/HLS_Conv/conv3x3_IPcore/solution1'.
INFO: [SYN 201-201] Setting up clock 'default' with a period of 10ns.
INFO: [HLS 200-10] Setting target device to 'xc7z020clg484-2'
INFO: [HLS 200-10] Analyzing design file 'src/pBox.cpp' ...
INFO: [HLS 200-10] Analyzing design file 'src/fpgaAcc.cpp' ...
INFO: [HLS 200-10] Validating synthesis directives ...
INFO: [HLS 200-111] Finished Checking Pragmas Time (s): cpu = 00:00:28 ; elapsed = 00:00:18 . Memory (MB): peak = 361.637 ; gain = 13.375 ; free physical = 409 ; free virtual = 32720
INFO: [HLS 200-111] Finished Linking Time (s): cpu = 00:00:30 ; elapsed = 00:00:20 . Memory (MB): peak = 361.637 ; gain = 13.375 ; free physical = 407 ; free virtual = 32720
INFO: [HLS 200-10] Starting code transformations ...
INFO: [XFORM 203-603] Inlining function 'MemoryController::setLayerConfig' into 'convolution_3x3' (src/fpgaAcc.cpp:77).
INFO: [XFORM 203-603] Inlining function 'ImageCache::setLayerConfig' into 'convolution_3x3' (src/fpgaAcc.cpp:78).
INFO: [XFORM 203-603] Inlining function 'WeightsCache::setLayerConfig' into 'convolution_3x3' (src/fpgaAcc.cpp:79).
INFO: [XFORM 203-603] Inlining function 'WeightsCache::get_WBRAM_addr' into 'WeightsCache::get_9_weights_to_buffer' (src/fpgaAcc.cpp:309).
INFO: [XFORM 203-603] Inlining function 'WeightsCache::get_WBRAM_addr' into 'WeightsCache::load_WBRAM_from_DRAM' (src/fpgaAcc.cpp:283).
INFO: [XFORM 203-603] Inlining function 'WeightsCache::load_WBRAM_from_DRAM' into 'convolution_3x3' (src/fpgaAcc.cpp:83).
INFO: [XFORM 203-603] Inlining function 'MemoryController::setPixelLoadRowOffset' into 'convolution_3x3' (src/fpgaAcc.cpp:94).
INFO: [XFORM 203-603] Inlining function 'MemoryController::setPixelLoadRowOffset' into 'convolution_3x3' (src/fpgaAcc.cpp:87).
INFO: [XFORM 203-603] Inlining function 'MemoryController::setPixelLoadRowOffset' into 'convolution_3x3' (src/fpgaAcc.cpp:85).
INFO: [XFORM 203-603] Inlining function 'MemoryController::setPixelLoadOffset' into 'ImageCache::loadRowDRAM_2_IBRAM' (src/fpgaAcc.cpp:332).
INFO: [XFORM 203-603] Inlining function 'MemoryController::loadInputChannelPixel' into 'ImageCache::loadPixelDRAM_2_IBRAM' (src/fpgaAcc.cpp:341).
INFO: [XFORM 203-603] Inlining function 'ImageCache::loadPixelDRAM_2_IBRAM' into 'ImageCache::loadRowDRAM_2_IBRAM' (src/fpgaAcc.cpp:333).
INFO: [XFORM 203-603] Inlining function 'ImageCache::loadRowDRAM_2_IBRAM' into 'convolution_3x3' (src/fpgaAcc.cpp:95).
INFO: [XFORM 203-603] Inlining function 'ImageCache::loadRowDRAM_2_IBRAM' into 'convolution_3x3' (src/fpgaAcc.cpp:88).
INFO: [XFORM 203-603] Inlining function 'ImageCache::loadRowDRAM_2_IBRAM' into 'convolution_3x3' (src/fpgaAcc.cpp:86).
INFO: [XFORM 203-603] Inlining function 'MemoryController::setPixelOutOffset' into 'convolution_3x3' (src/fpgaAcc.cpp:99).
INFO: [XFORM 203-603] Inlining function 'ImageCache::calcu_IBRAM_row_offset' into 'ProcessingElement::loadPixel_buffer' (src/fpgaAcc.cpp:209).
INFO: [XFORM 203-603] Inlining function 'ImageCache::get_IBRAM_Pixel' into 'ProcessingElement::loadPixel_buffer' (src/fpgaAcc.cpp:213).
INFO: [XFORM 203-603] Inlining function 'ProcessingElement::loadPixel_buffer' into 'ProcessingElement::processInputChannel' (src/fpgaAcc.cpp:230).
INFO: [XFORM 203-603] Inlining function 'WeightsCache::get_9_weights_to_buffer' into 'ProcessingElement::processAll_channelOut' (src/fpgaAcc.cpp:246).
INFO: [XFORM 203-603] Inlining function 'ProcessingElement::macc2d' into 'ProcessingElement::processAll_channelOut' (src/fpgaAcc.cpp:248).
INFO: [XFORM 203-603] Inlining function 'OutputCache::setOutChannel' into 'OutputCache::accumulateChannel' (src/fpgaAcc.cpp:386).
INFO: [XFORM 203-603] Inlining function 'OutputCache::setOutChannel' into 'ProcessingElement::processAll_channelOut' (src/fpgaAcc.cpp:251).
INFO: [XFORM 203-603] Inlining function 'OutputCache::getOutChannel' into 'OutputCache::accumulateChannel' (src/fpgaAcc.cpp:384).
INFO: [XFORM 203-603] Inlining function 'OutputCache::accumulateChannel' into 'ProcessingElement::processAll_channelOut' (src/fpgaAcc.cpp:253).
INFO: [XFORM 203-603] Inlining function 'MemoryController::writeBackOutputChannel' into 'convolution_3x3' (src/fpgaAcc.cpp:109).
INFO: [HLS 200-111] Finished Standard Transforms Time (s): cpu = 00:00:31 ; elapsed = 00:00:21 . Memory (MB): peak = 361.926 ; gain = 13.664 ; free physical = 397 ; free virtual = 32712
INFO: [HLS 200-10] Checking synthesizability ...
INFO: [XFORM 203-602] Inlining function 'ImageCache::writeNextChannelPixel_2_IBRAM' into 'convolution_3x3' (src/fpgaAcc.cpp:342->src/fpgaAcc.cpp:333->src/fpgaAcc.cpp:86) automatically.
INFO: [HLS 200-111] Finished Checking Synthesizability Time (s): cpu = 00:00:31 ; elapsed = 00:00:21 . Memory (MB): peak = 361.926 ; gain = 13.664 ; free physical = 394 ; free virtual = 32710
INFO: [XFORM 203-502] Unrolling all sub-loops inside loop 'L_CH_OUT' (src/fpgaAcc.cpp:240) in function 'ProcessingElement::processAll_channelOut' for pipelining.
INFO: [XFORM 203-501] Unrolling loop 'Loop-1.1' (src/fpgaAcc.cpp:310) in function 'ProcessingElement::processAll_channelOut' completely.
INFO: [XFORM 203-501] Unrolling loop 'L_MACC_multiply' (src/fpgaAcc.cpp:190) in function 'ProcessingElement::processAll_channelOut' completely.
INFO: [XFORM 203-501] Unrolling loop 'L_MACC_accumulate' (src/fpgaAcc.cpp:195) in function 'ProcessingElement::processAll_channelOut' completely.
INFO: [XFORM 203-101] Partitioning array 'pixel_buffer' (src/fpgaAcc.cpp:228) in dimension 1 completely.
INFO: [XFORM 203-101] Partitioning array 'weights_local' (src/fpgaAcc.cpp:243) in dimension 1 completely.
INFO: [XFORM 203-101] Partitioning array 'WeightsCache::WBRAM' in dimension 1 completely.
INFO: [XFORM 203-101] Partitioning array 'multresult' (src/fpgaAcc.cpp:187) in dimension 1 completely.
INFO: [XFORM 203-101] Partitioning array 'OutputCache::OBRAM' in dimension 1 with a cyclic factor 8.
INFO: [XFORM 203-101] Partitioning array 'WeightsCache::WBRAM.0' in dimension 2 completely.
INFO: [XFORM 203-101] Partitioning array 'WeightsCache::WBRAM.1' in dimension 2 completely.
INFO: [XFORM 203-101] Partitioning array 'WeightsCache::WBRAM.2' in dimension 2 completely.
INFO: [XFORM 203-101] Partitioning array 'WeightsCache::WBRAM.3' in dimension 2 completely.
INFO: [XFORM 203-101] Partitioning array 'WeightsCache::WBRAM.4' in dimension 2 completely.
INFO: [XFORM 203-101] Partitioning array 'WeightsCache::WBRAM.5' in dimension 2 completely.
INFO: [XFORM 203-101] Partitioning array 'WeightsCache::WBRAM.6' in dimension 2 completely.
INFO: [XFORM 203-101] Partitioning array 'WeightsCache::WBRAM.7' in dimension 2 completely.
INFO: [XFORM 203-602] Inlining function 'ImageCache::writeNextChannelPixel_2_IBRAM' into 'convolution_3x3' (src/fpgaAcc.cpp:342->src/fpgaAcc.cpp:333->src/fpgaAcc.cpp:86) automatically.
INFO: [XFORM 203-622] Instantiating function 'ProcessingElement::processInputChannel'(src/fpgaAcc.cpp:221) to 'ProcessingElement::processInputChannel.0' at call site (src/fpgaAcc.cpp:103) by setting 'cur_ci' to 'cur_channel_in'.
INFO: [XFORM 203-401] Performing if-conversion on hyperblock from (src/fpgaAcc.cpp:211:60) to (src/fpgaAcc.cpp:211:43) in function 'ProcessingElement::processInputChannel.0'... converting 10 basic blocks.
INFO: [HLS 200-111] Finished Pre-synthesis Time (s): cpu = 00:00:33 ; elapsed = 00:00:23 . Memory (MB): peak = 489.633 ; gain = 141.371 ; free physical = 366 ; free virtual = 32685
WARNING: [XFORM 203-542] Cannot flatten a loop nest 'Loop-1.1' (src/fpgaAcc.cpp:282:18) in function 'convolution_3x3' :
the outer loop is not a perfect loop.
WARNING: [XFORM 203-542] Cannot flatten a loop nest 'Loop-1' (src/fpgaAcc.cpp:279:18) in function 'convolution_3x3' :
the outer loop is not a perfect loop.
WARNING: [XFORM 203-542] Cannot flatten a loop nest 'L_DRAM_PRELOADROW_X' (src/fpgaAcc.cpp:331:77) in function 'convolution_3x3' :
the outer loop is not a perfect loop.
WARNING: [XFORM 203-542] Cannot flatten a loop nest 'L_DRAM_PRELOADROW_X' (src/fpgaAcc.cpp:331:77) in function 'convolution_3x3' :
the outer loop is not a perfect loop.
WARNING: [XFORM 203-542] Cannot flatten a loop nest 'L_DRAM_PRELOADROW_X' (src/fpgaAcc.cpp:331:77) in function 'convolution_3x3' :
the outer loop is not a perfect loop.
WARNING: [XFORM 203-542] Cannot flatten a loop nest 'Loop-4.1' (src/fpgaAcc.cpp:93:3) in function 'convolution_3x3' :
the outer loop is not a perfect loop.
WARNING: [XFORM 203-542] Cannot flatten a loop nest 'row_loop' (src/fpgaAcc.cpp:91:85) in function 'convolution_3x3' :
more than one sub loop.
WARNING: [XFORM 203-631] Renaming function 'ProcessingElement::processInputChannel.0' to 'processInputChannel.' (src/fpgaAcc.cpp:207:43)
WARNING: [XFORM 203-631] Renaming function 'ProcessingElement::processAll_channelOut' to 'processAll_channelOu' (src/fpgaAcc.cpp:192:50)
WARNING: [XFORM 203-631] Renaming function 'MemoryController::load_weight_2_reg' to 'load_weight_2_reg' (src/fpgaAcc.cpp:175)
INFO: [HLS 200-111] Finished Architecture Synthesis Time (s): cpu = 00:00:35 ; elapsed = 00:00:25 . Memory (MB): peak = 489.633 ; gain = 141.371 ; free physical = 331 ; free virtual = 32650
INFO: [HLS 200-10] Starting hardware synthesis ...
INFO: [HLS 200-10] Synthesizing 'convolution_3x3' ...
WARNING: [SYN 201-103] Legalizing function name 'reg<float>' to 'reg_float_s'.
WARNING: [SYN 201-103] Legalizing function name 'processInputChannel.' to 'processInputChannel_s'.
WARNING: [SYN 201-303] Cannot apply functional unit assignment of 'MulnS' on 'weight_DRAM_ptr_offset1', which is not an operation.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-42] -- Implementing module 'reg_float_s'
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [SCHED 204-11] Starting scheduling ...
INFO: [SCHED 204-61] Pipelining function 'reg<float>'.
INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2.
INFO: [SCHED 204-11] Finished scheduling.
INFO: [HLS 200-111] Elapsed time: 25.46 seconds; current allocated memory: 122.443 MB.
INFO: [BIND 205-100] Starting micro-architecture generation ...
INFO: [BIND 205-101] Performing variable lifetime analysis.
INFO: [BIND 205-101] Exploring resource sharing.
INFO: [BIND 205-101] Binding ...
INFO: [BIND 205-100] Finished micro-architecture generation.
INFO: [HLS 200-111] Elapsed time: 0.02 seconds; current allocated memory: 122.503 MB.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-42] -- Implementing module 'load_weight_2_reg'
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [SCHED 204-11] Starting scheduling ...
INFO: [SCHED 204-61] Pipelining function 'load_weight_2_reg'.
INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 10.
INFO: [SCHED 204-11] Finished scheduling.
INFO: [HLS 200-111] Elapsed time: 0.04 seconds; current allocated memory: 122.709 MB.
INFO: [BIND 205-100] Starting micro-architecture generation ...
INFO: [BIND 205-101] Performing variable lifetime analysis.
INFO: [BIND 205-101] Exploring resource sharing.
INFO: [BIND 205-101] Binding ...
INFO: [BIND 205-100] Finished micro-architecture generation.
INFO: [HLS 200-111] Elapsed time: 0.05 seconds; current allocated memory: 122.805 MB.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-42] -- Implementing module 'processAll_channelOu'
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [SCHED 204-11] Starting scheduling ...
INFO: [SCHED 204-61] Pipelining loop 'L_CH_OUT'.
WARNING: [SCHED 204-68] Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1)
between 'store' operation (src/fpgaAcc.cpp:397->src/fpgaAcc.cpp:386->src/fpgaAcc.cpp:253) of variable 'new_ch', src/fpgaAcc.cpp:385->src/fpgaAcc.cpp:253 on array 'OBRAM_0' and 'load' operation ('OBRAM_0_load', src/fpgaAcc.cpp:391->src/fpgaAcc.cpp:384->src/fpgaAcc.cpp:253) on array 'OBRAM_0'.
WARNING: [SCHED 204-68] Unable to enforce a carried dependence constraint (II = 2, distance = 1, offset = 1)
between 'store' operation (src/fpgaAcc.cpp:397->src/fpgaAcc.cpp:386->src/fpgaAcc.cpp:253) of variable 'new_ch', src/fpgaAcc.cpp:385->src/fpgaAcc.cpp:253 on array 'OBRAM_0' and 'load' operation ('OBRAM_0_load', src/fpgaAcc.cpp:391->src/fpgaAcc.cpp:384->src/fpgaAcc.cpp:253) on array 'OBRAM_0'.
WARNING: [SCHED 204-68] Unable to enforce a carried dependence constraint (II = 3, distance = 1, offset = 1)
between 'store' operation (src/fpgaAcc.cpp:397->src/fpgaAcc.cpp:386->src/fpgaAcc.cpp:253) of variable 'new_ch', src/fpgaAcc.cpp:385->src/fpgaAcc.cpp:253 on array 'OBRAM_0' and 'load' operation ('OBRAM_0_load', src/fpgaAcc.cpp:391->src/fpgaAcc.cpp:384->src/fpgaAcc.cpp:253) on array 'OBRAM_0'.
WARNING: [SCHED 204-68] Unable to enforce a carried dependence constraint (II = 4, distance = 1, offset = 1)
between 'store' operation (src/fpgaAcc.cpp:397->src/fpgaAcc.cpp:386->src/fpgaAcc.cpp:253) of variable 'new_ch', src/fpgaAcc.cpp:385->src/fpgaAcc.cpp:253 on array 'OBRAM_0' and 'load' operation ('OBRAM_0_load', src/fpgaAcc.cpp:391->src/fpgaAcc.cpp:384->src/fpgaAcc.cpp:253) on array 'OBRAM_0'.
WARNING: [SCHED 204-68] Unable to enforce a carried dependence constraint (II = 5, distance = 1, offset = 1)
between 'store' operation (src/fpgaAcc.cpp:397->src/fpgaAcc.cpp:386->src/fpgaAcc.cpp:253) of variable 'new_ch', src/fpgaAcc.cpp:385->src/fpgaAcc.cpp:253 on array 'OBRAM_0' and 'load' operation ('OBRAM_0_load', src/fpgaAcc.cpp:391->src/fpgaAcc.cpp:384->src/fpgaAcc.cpp:253) on array 'OBRAM_0'.
INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 6, Depth = 49.
WARNING: [SCHED 204-21] Estimated clock period (13.1928ns) exceeds the target (target clock period: 10ns, clock uncertainty: 1.25ns, effective delay budget: 8.75ns).
WARNING: [SCHED 204-21] The critical path consists of the following:
'load' operation ('OBRAM_0_load', src/fpgaAcc.cpp:391->src/fpgaAcc.cpp:384->src/fpgaAcc.cpp:253) on array 'OBRAM_0' (2.77 ns)
'mux' operation ('old_ch', src/fpgaAcc.cpp:391->src/fpgaAcc.cpp:384->src/fpgaAcc.cpp:253) (1.83 ns)
'fadd' operation ('new_ch', src/fpgaAcc.cpp:385->src/fpgaAcc.cpp:253) (8.59 ns)
INFO: [SCHED 204-11] Finished scheduling.
INFO: [HLS 200-111] Elapsed time: 0.73 seconds; current allocated memory: 124.290 MB.
INFO: [BIND 205-100] Starting micro-architecture generation ...
INFO: [BIND 205-101] Performing variable lifetime analysis.
INFO: [BIND 205-101] Exploring resource sharing.
INFO: [BIND 205-101] Binding ...
INFO: [BIND 205-100] Finished micro-architecture generation.
INFO: [HLS 200-111] Elapsed time: 0.67 seconds; current allocated memory: 125.896 MB.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-42] -- Implementing module 'processInputChannel_s'
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [SCHED 204-11] Starting scheduling ...
INFO: [SCHED 204-11] Finished scheduling.
INFO: [HLS 200-111] Elapsed time: 0.73 seconds; current allocated memory: 126.433 MB.
INFO: [BIND 205-100] Starting micro-architecture generation ...
INFO: [BIND 205-101] Performing variable lifetime analysis.
INFO: [BIND 205-101] Exploring resource sharing.
INFO: [BIND 205-101] Binding ...
INFO: [BIND 205-100] Finished micro-architecture generation.
INFO: [HLS 200-111] Elapsed time: 0.33 seconds; current allocated memory: 127.188 MB.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-42] -- Implementing module 'convolution_3x3'
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [SCHED 204-11] Starting scheduling ...
INFO: [SCHED 204-61] Pipelining loop 'Loop 1.1.1'.
INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 12.
INFO: [SCHED 204-61] Pipelining loop 'L_PRELOAD_PIXEL_FROM_DRAM'.
INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 14.
INFO: [SCHED 204-61] Pipelining loop 'L_PRELOAD_PIXEL_FROM_DRAM'.
INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 14.
INFO: [SCHED 204-61] Pipelining loop 'L_PRELOAD_PIXEL_FROM_DRAM'.
INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 14.
INFO: [SCHED 204-11] Finished scheduling.
INFO: [HLS 200-111] Elapsed time: 1.04 seconds; current allocated memory: 130.198 MB.
INFO: [BIND 205-100] Starting micro-architecture generation ...
INFO: [BIND 205-101] Performing variable lifetime analysis.
INFO: [BIND 205-101] Exploring resource sharing.
INFO: [BIND 205-101] Binding ...
INFO: [BIND 205-100] Finished micro-architecture generation.
INFO: [HLS 200-111] Elapsed time: 1.34 seconds; current allocated memory: 133.203 MB.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-10] -- Generating RTL for module 'reg_float_s'
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [RTGEN 206-100] Finished creating RTL model for 'reg_float_s'.
INFO: [HLS 200-111] Elapsed time: 1.01 seconds; current allocated memory: 133.541 MB.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-10] -- Generating RTL for module 'load_weight_2_reg'
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [RTGEN 206-100] Finished creating RTL model for 'load_weight_2_reg'.
INFO: [HLS 200-111] Elapsed time: 0.03 seconds; current allocated memory: 134.166 MB.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-10] -- Generating RTL for module 'processAll_channelOu'
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_fadd_32ns_32ns_32_4_full_dsp_1' to 'convolution_3x3_fbkb' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_fmul_32ns_32ns_32_3_max_dsp_1' to 'convolution_3x3_fcud' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_mux_83_32_1_1' to 'convolution_3x3_mdEe' due to the length limit 20
INFO: [RTGEN 206-100] Generating core module 'convolution_3x3_fbkb': 2 instance(s).
INFO: [RTGEN 206-100] Generating core module 'convolution_3x3_fcud': 2 instance(s).
INFO: [RTGEN 206-100] Generating core module 'convolution_3x3_mdEe': 10 instance(s).
INFO: [RTGEN 206-100] Finished creating RTL model for 'processAll_channelOu'.
INFO: [HLS 200-111] Elapsed time: 0.18 seconds; current allocated memory: 136.549 MB.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-10] -- Generating RTL for module 'processInputChannel_s'
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_mul_32s_32s_32_3_1' to 'convolution_3x3_meOg' due to the length limit 20
INFO: [RTGEN 206-100] Generating core module 'convolution_3x3_meOg': 2 instance(s).
INFO: [RTGEN 206-100] Finished creating RTL model for 'processInputChannel_s'.
INFO: [HLS 200-111] Elapsed time: 1.01 seconds; current allocated memory: 143.526 MB.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-10] -- Generating RTL for module 'convolution_3x3'
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [RTGEN 206-500] Setting interface mode on port 'convolution_3x3/memorybus' to 'm_axi'.
INFO: [RTGEN 206-500] Setting interface mode on port 'convolution_3x3/inHight' to 's_axilite & ap_none' (register).
INFO: [RTGEN 206-500] Setting interface mode on port 'convolution_3x3/inWidth' to 's_axilite & ap_none' (register).
INFO: [RTGEN 206-500] Setting interface mode on port 'convolution_3x3/inChanNum' to 's_axilite & ap_none' (register).
INFO: [RTGEN 206-500] Setting interface mode on port 'convolution_3x3/outHight' to 's_axilite & ap_none' (register).
INFO: [RTGEN 206-500] Setting interface mode on port 'convolution_3x3/outWidth' to 's_axilite & ap_none' (register).
INFO: [RTGEN 206-500] Setting interface mode on port 'convolution_3x3/OutChanNum' to 's_axilite & ap_none' (register).
INFO: [RTGEN 206-500] Setting interface mode on port 'convolution_3x3/stride' to 's_axilite & ap_none' (register).
INFO: [RTGEN 206-500] Setting interface mode on port 'convolution_3x3/weight_ptr' to 's_axilite & ap_none'.
INFO: [RTGEN 206-500] Setting interface mode on port 'convolution_3x3/input_ptr' to 's_axilite & ap_none'.
INFO: [RTGEN 206-500] Setting interface mode on port 'convolution_3x3/output_ptr' to 's_axilite & ap_none'.
INFO: [RTGEN 206-500] Setting interface mode on function 'convolution_3x3' to 'ap_ctrl_hs'.
WARNING: [RTGEN 206-101] Register 'MemoryController_ou_5' is power-on initialization.
WARNING: [RTGEN 206-101] Global scalar 'MemoryController_ou_5' will not be exposed as RTL port.
WARNING: [RTGEN 206-101] Register 'MemoryController_ou' is power-on initialization.
WARNING: [RTGEN 206-101] Global scalar 'MemoryController_ou' will not be exposed as RTL port.
WARNING: [RTGEN 206-101] Register 'MemoryController_ou_3' is power-on initialization.
WARNING: [RTGEN 206-101] Global scalar 'MemoryController_ou_3' will not be exposed as RTL port.
WARNING: [RTGEN 206-101] Register 'MemoryController_ou_4' is power-on initialization.
WARNING: [RTGEN 206-101] Global scalar 'MemoryController_ou_4' will not be exposed as RTL port.
WARNING: [RTGEN 206-101] Register 'MemoryController_in' is power-on initialization.
WARNING: [RTGEN 206-101] Global scalar 'MemoryController_in' will not be exposed as RTL port.
WARNING: [RTGEN 206-101] Register 'MemoryController_st' is power-on initialization.
WARNING: [RTGEN 206-101] Global scalar 'MemoryController_st' will not be exposed as RTL port.
WARNING: [RTGEN 206-101] Register 'MemoryController_in_1' is power-on initialization.
WARNING: [RTGEN 206-101] Global scalar 'MemoryController_in_1' will not be exposed as RTL port.
WARNING: [RTGEN 206-101] Register 'MemoryController_cu_1' is power-on initialization.
WARNING: [RTGEN 206-101] Global scalar 'MemoryController_cu_1' will not be exposed as RTL port.
WARNING: [RTGEN 206-101] Register 'MemoryController_cu' is power-on initialization.
WARNING: [RTGEN 206-101] Global scalar 'MemoryController_cu' will not be exposed as RTL port.
WARNING: [RTGEN 206-101] Global scalar 'ImageCache_in_heigh' will not be exposed as RTL port.
WARNING: [RTGEN 206-101] Register 'ImageCache_in_width' is power-on initialization.
WARNING: [RTGEN 206-101] Global scalar 'ImageCache_in_width' will not be exposed as RTL port.
WARNING: [RTGEN 206-101] Register 'ImageCache_in_Chann_1' is power-on initialization.
WARNING: [RTGEN 206-101] Global scalar 'ImageCache_in_Chann_1' will not be exposed as RTL port.
WARNING: [RTGEN 206-101] Global scalar 'ImageCache_in_Chann' will not be exposed as RTL port.
WARNING: [RTGEN 206-101] Register 'ImageCache_MAX_IBRA' is power-on initialization.
WARNING: [RTGEN 206-101] Global scalar 'ImageCache_MAX_IBRA' will not be exposed as RTL port.
WARNING: [RTGEN 206-101] Register 'ImageCache_cur_IBRA' is power-on initialization.
WARNING: [RTGEN 206-101] Global scalar 'ImageCache_cur_IBRA' will not be exposed as RTL port.
WARNING: [RTGEN 206-101] Register 'WeightsCache_outCha' is power-on initialization.
WARNING: [RTGEN 206-101] Global scalar 'WeightsCache_outCha' will not be exposed as RTL port.
WARNING: [RTGEN 206-101] Register 'WeightsCache_inChan' is power-on initialization.
WARNING: [RTGEN 206-101] Global scalar 'WeightsCache_inChan' will not be exposed as RTL port.
WARNING: [RTGEN 206-101] Register 'MemoryController_pi' is power-on initialization.
WARNING: [RTGEN 206-101] Global scalar 'MemoryController_pi' will not be exposed as RTL port.
WARNING: [RTGEN 206-101] Register 'MemoryController_lo' is power-on initialization.
WARNING: [RTGEN 206-101] Global scalar 'MemoryController_lo' will not be exposed as RTL port.
WARNING: [RTGEN 206-101] Global array 'ImageCache_IBRAM' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_ImageCache_IBRAM' to 'convolution_3x3_IfYi' due to the length limit 20
WARNING: [RTGEN 206-101] Register 'MemoryController_pe' is power-on initialization.
WARNING: [RTGEN 206-101] Global scalar 'MemoryController_pe' will not be exposed as RTL port.
WARNING: [RTGEN 206-101] Global array 'WBRAM_0_0' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_0_0' to 'convolution_3x3_Wg8j' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_1_0' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_1_0' to 'convolution_3x3_Whbi' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_2_0' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_2_0' to 'convolution_3x3_Wibs' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_3_0' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_3_0' to 'convolution_3x3_WjbC' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_4_0' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_4_0' to 'convolution_3x3_WkbM' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_5_0' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_5_0' to 'convolution_3x3_WlbW' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_6_0' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_6_0' to 'convolution_3x3_Wmb6' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_7_0' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_7_0' to 'convolution_3x3_Wncg' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_0_1' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_0_1' to 'convolution_3x3_Wocq' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_1_1' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_1_1' to 'convolution_3x3_WpcA' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_2_1' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_2_1' to 'convolution_3x3_WqcK' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_3_1' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_3_1' to 'convolution_3x3_WrcU' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_4_1' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_4_1' to 'convolution_3x3_Wsc4' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_5_1' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_5_1' to 'convolution_3x3_Wtde' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_6_1' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_6_1' to 'convolution_3x3_Wudo' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_7_1' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_7_1' to 'convolution_3x3_Wvdy' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_0_2' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_0_2' to 'convolution_3x3_WwdI' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_1_2' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_1_2' to 'convolution_3x3_WxdS' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_2_2' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_2_2' to 'convolution_3x3_Wyd2' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_3_2' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_3_2' to 'convolution_3x3_Wzec' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_4_2' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_4_2' to 'convolution_3x3_WAem' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_5_2' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_5_2' to 'convolution_3x3_WBew' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_6_2' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_6_2' to 'convolution_3x3_WCeG' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_7_2' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_7_2' to 'convolution_3x3_WDeQ' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_0_3' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_0_3' to 'convolution_3x3_WEe0' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_1_3' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_1_3' to 'convolution_3x3_WFfa' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_2_3' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_2_3' to 'convolution_3x3_WGfk' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_3_3' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_3_3' to 'convolution_3x3_WHfu' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_4_3' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_4_3' to 'convolution_3x3_WIfE' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_5_3' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_5_3' to 'convolution_3x3_WJfO' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_6_3' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_6_3' to 'convolution_3x3_WKfY' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_7_3' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_7_3' to 'convolution_3x3_WLf8' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_0_4' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_0_4' to 'convolution_3x3_WMgi' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_1_4' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_1_4' to 'convolution_3x3_WNgs' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_2_4' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_2_4' to 'convolution_3x3_WOgC' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_3_4' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_3_4' to 'convolution_3x3_WPgM' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_4_4' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_4_4' to 'convolution_3x3_WQgW' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_5_4' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_5_4' to 'convolution_3x3_WRg6' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_6_4' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_6_4' to 'convolution_3x3_WShg' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_7_4' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_7_4' to 'convolution_3x3_WThq' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_0_5' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_0_5' to 'convolution_3x3_WUhA' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_1_5' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_1_5' to 'convolution_3x3_WVhK' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_2_5' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_2_5' to 'convolution_3x3_WWhU' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_3_5' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_3_5' to 'convolution_3x3_WXh4' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_4_5' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_4_5' to 'convolution_3x3_WYie' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_5_5' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_5_5' to 'convolution_3x3_WZio' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_6_5' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_6_5' to 'convolution_3x3_W0iy' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_7_5' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_7_5' to 'convolution_3x3_W1iI' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_0_6' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_0_6' to 'convolution_3x3_W2iS' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_1_6' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_1_6' to 'convolution_3x3_W3i2' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_2_6' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_2_6' to 'convolution_3x3_W4jc' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_3_6' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_3_6' to 'convolution_3x3_W5jm' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_4_6' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_4_6' to 'convolution_3x3_W6jw' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_5_6' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_5_6' to 'convolution_3x3_W7jG' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_6_6' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_6_6' to 'convolution_3x3_W8jQ' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_7_6' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_7_6' to 'convolution_3x3_W9j0' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_0_7' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_0_7' to 'convolution_3x3_Wbak' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_1_7' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_1_7' to 'convolution_3x3_Wbbk' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_2_7' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_2_7' to 'convolution_3x3_Wbck' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_3_7' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_3_7' to 'convolution_3x3_Wbdk' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_4_7' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_4_7' to 'convolution_3x3_Wbek' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_5_7' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_5_7' to 'convolution_3x3_Wbfk' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_6_7' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_6_7' to 'convolution_3x3_Wbgk' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_7_7' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_7_7' to 'convolution_3x3_Wbhl' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_0_8' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_0_8' to 'convolution_3x3_Wbil' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_1_8' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_1_8' to 'convolution_3x3_Wbjl' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_2_8' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_2_8' to 'convolution_3x3_Wbkl' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_3_8' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_3_8' to 'convolution_3x3_Wbll' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_4_8' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_4_8' to 'convolution_3x3_Wbml' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_5_8' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_5_8' to 'convolution_3x3_Wbnm' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_6_8' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_6_8' to 'convolution_3x3_Wbom' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_7_8' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_7_8' to 'convolution_3x3_Wbpm' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'OBRAM_0' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_OBRAM_0' to 'convolution_3x3_Obqm' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'OBRAM_1' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_OBRAM_1' to 'convolution_3x3_Obrm' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'OBRAM_2' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_OBRAM_2' to 'convolution_3x3_Obsm' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'OBRAM_3' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_OBRAM_3' to 'convolution_3x3_Obtn' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'OBRAM_4' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_OBRAM_4' to 'convolution_3x3_Obun' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'OBRAM_5' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_OBRAM_5' to 'convolution_3x3_Obvn' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'OBRAM_6' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_OBRAM_6' to 'convolution_3x3_Obwn' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'OBRAM_7' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_OBRAM_7' to 'convolution_3x3_Obxn' due to the length limit 20
INFO: [RTGEN 206-100] Bundling port 'weight_ptr', 'input_ptr' and 'output_ptr' to AXI-Lite port AXILiteS.
INFO: [RTGEN 206-100] Bundling port 'inHight', 'inWidth', 'inChanNum', 'outHight', 'outWidth', 'OutChanNum' and 'stride' to AXI-Lite port axilite.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_mul_32s_5ns_32_3_1' to 'convolution_3x3_mbyn' due to the length limit 20
INFO: [RTGEN 206-100] Generating core module 'convolution_3x3_mbyn': 1 instance(s).
INFO: [RTGEN 206-100] Generating core module 'convolution_3x3_mdEe': 1 instance(s).
INFO: [RTGEN 206-100] Generating core module 'convolution_3x3_meOg': 13 instance(s).
INFO: [RTGEN 206-100] Finished creating RTL model for 'convolution_3x3'.
INFO: [HLS 200-111] Elapsed time: 3.55 seconds; current allocated memory: 153.417 MB.
INFO: [RTMG 210-282] Generating pipelined core: 'convolution_3x3_meOg_MulnS_0'
INFO: [RTMG 210-282] Generating pipelined core: 'convolution_3x3_mbyn_MulnS_1'
INFO: [RTMG 210-278] Implementing memory 'convolution_3x3_IfYi_ram (RAM_S2P_BRAM)' using block RAMs with power-on initialization.
INFO: [RTMG 210-278] Implementing memory 'convolution_3x3_Wg8j_ram (RAM_S2P_BRAM)' using block RAMs with power-on initialization.
INFO: [RTMG 210-278] Implementing memory 'convolution_3x3_Obqm_ram (RAM_T2P_BRAM)' using block RAMs with power-on initialization.
INFO: [HLS 200-111] Finished generating all RTL models Time (s): cpu = 00:00:47 ; elapsed = 00:00:41 . Memory (MB): peak = 553.633 ; gain = 205.371 ; free physical = 259 ; free virtual = 32598
INFO: [SYSC 207-301] Generating SystemC RTL for convolution_3x3.
INFO: [VHDL 208-304] Generating VHDL RTL for convolution_3x3.
INFO: [VLOG 209-307] Generating Verilog RTL for convolution_3x3.
INFO: [HLS 200-112] Total elapsed time: 40.99 seconds; peak allocated memory: 153.417 MB.
Finished C synthesis.
时钟周期的错误主要来自于OBRAM的accumulate_channel
二、加回DATAFLOW与UNROLL
2.1 N_PE=8
正常运行，并且时钟周期还回归了正常，但是硬件空间资源超出。
Starting C synthesis ...
/mnt/workspace/Xilinx/Vivado/2017.4/bin/vivado_hls /home/osrc/Desktop/document/conv_Core/HLS_Conv/conv3x3_IPcore/solution1/csynth.tcl
INFO: [HLS 200-10] Running '/mnt/workspace/Xilinx/Vivado/2017.4/bin/unwrapped/lnx64.o/vivado_hls'
INFO: [HLS 200-10] For user 'osrc' on host 'osrc-virtual-machine' (Linux_x86_64 version 4.13.0-32-generic) on Wed Dec 12 20:21:17 CST 2018
INFO: [HLS 200-10] On os Ubuntu 16.04.3 LTS
INFO: [HLS 200-10] In directory '/home/osrc/Desktop/document/conv_Core/HLS_Conv'
INFO: [HLS 200-10] Opening project '/home/osrc/Desktop/document/conv_Core/HLS_Conv/conv3x3_IPcore'.
INFO: [HLS 200-10] Adding design file 'src/fpgaAcc.cpp' to the project
INFO: [HLS 200-10] Adding design file 'src/fpgaAcc.hpp' to the project
INFO: [HLS 200-10] Adding design file 'src/pBox.cpp' to the project
INFO: [HLS 200-10] Adding design file 'src/pBox.h' to the project
INFO: [HLS 200-10] Adding test bench file 'src/test_convBench.cpp' to the project
INFO: [HLS 200-10] Opening solution '/home/osrc/Desktop/document/conv_Core/HLS_Conv/conv3x3_IPcore/solution1'.
INFO: [SYN 201-201] Setting up clock 'default' with a period of 10ns.
INFO: [HLS 200-10] Setting target device to 'xc7z020clg484-2'
INFO: [HLS 200-10] Analyzing design file 'src/pBox.cpp' ...
INFO: [HLS 200-10] Analyzing design file 'src/fpgaAcc.cpp' ...
INFO: [HLS 200-10] Validating synthesis directives ...
INFO: [HLS 200-111] Finished Checking Pragmas Time (s): cpu = 00:00:31 ; elapsed = 00:00:20 . Memory (MB): peak = 361.637 ; gain = 13.375 ; free physical = 354 ; free virtual = 32667
INFO: [HLS 200-111] Finished Linking Time (s): cpu = 00:00:33 ; elapsed = 00:00:22 . Memory (MB): peak = 361.637 ; gain = 13.375 ; free physical = 352 ; free virtual = 32667
INFO: [HLS 200-10] Starting code transformations ...
INFO: [XFORM 203-603] Inlining function 'MemoryController::setLayerConfig' into 'convolution_3x3' (src/fpgaAcc.cpp:77).
INFO: [XFORM 203-603] Inlining function 'ImageCache::setLayerConfig' into 'convolution_3x3' (src/fpgaAcc.cpp:78).
INFO: [XFORM 203-603] Inlining function 'WeightsCache::setLayerConfig' into 'convolution_3x3' (src/fpgaAcc.cpp:79).
INFO: [XFORM 203-603] Inlining function 'WeightsCache::get_WBRAM_addr' into 'WeightsCache::get_9_weights_to_buffer' (src/fpgaAcc.cpp:309).
INFO: [XFORM 203-603] Inlining function 'WeightsCache::get_WBRAM_addr' into 'WeightsCache::load_WBRAM_from_DRAM' (src/fpgaAcc.cpp:283).
INFO: [XFORM 203-603] Inlining function 'WeightsCache::load_WBRAM_from_DRAM' into 'convolution_3x3' (src/fpgaAcc.cpp:83).
INFO: [XFORM 203-603] Inlining function 'MemoryController::setPixelLoadRowOffset' into 'convolution_3x3' (src/fpgaAcc.cpp:94).
INFO: [XFORM 203-603] Inlining function 'MemoryController::setPixelLoadRowOffset' into 'convolution_3x3' (src/fpgaAcc.cpp:87).
INFO: [XFORM 203-603] Inlining function 'MemoryController::setPixelLoadRowOffset' into 'convolution_3x3' (src/fpgaAcc.cpp:85).
INFO: [XFORM 203-603] Inlining function 'MemoryController::setPixelLoadOffset' into 'ImageCache::loadRowDRAM_2_IBRAM' (src/fpgaAcc.cpp:332).
INFO: [XFORM 203-603] Inlining function 'MemoryController::loadInputChannelPixel' into 'ImageCache::loadPixelDRAM_2_IBRAM' (src/fpgaAcc.cpp:341).
INFO: [XFORM 203-603] Inlining function 'ImageCache::loadPixelDRAM_2_IBRAM' into 'ImageCache::loadRowDRAM_2_IBRAM' (src/fpgaAcc.cpp:333).
INFO: [XFORM 203-603] Inlining function 'ImageCache::loadRowDRAM_2_IBRAM' into 'convolution_3x3' (src/fpgaAcc.cpp:95).
INFO: [XFORM 203-603] Inlining function 'ImageCache::loadRowDRAM_2_IBRAM' into 'convolution_3x3' (src/fpgaAcc.cpp:88).
INFO: [XFORM 203-603] Inlining function 'ImageCache::loadRowDRAM_2_IBRAM' into 'convolution_3x3' (src/fpgaAcc.cpp:86).
INFO: [XFORM 203-603] Inlining function 'MemoryController::setPixelOutOffset' into 'convolution_3x3' (src/fpgaAcc.cpp:99).
INFO: [XFORM 203-603] Inlining function 'ImageCache::calcu_IBRAM_row_offset' into 'ProcessingElement::loadPixel_buffer' (src/fpgaAcc.cpp:209).
INFO: [XFORM 203-603] Inlining function 'ImageCache::get_IBRAM_Pixel' into 'ProcessingElement::loadPixel_buffer' (src/fpgaAcc.cpp:213).
INFO: [XFORM 203-603] Inlining function 'ProcessingElement::loadPixel_buffer' into 'ProcessingElement::processInputChannel' (src/fpgaAcc.cpp:230).
INFO: [XFORM 203-603] Inlining function 'WeightsCache::get_9_weights_to_buffer' into 'ProcessingElement::processAll_channelOut' (src/fpgaAcc.cpp:246).
INFO: [XFORM 203-603] Inlining function 'ProcessingElement::macc2d' into 'ProcessingElement::processAll_channelOut' (src/fpgaAcc.cpp:248).
INFO: [XFORM 203-603] Inlining function 'OutputCache::setOutChannel' into 'OutputCache::accumulateChannel' (src/fpgaAcc.cpp:386).
INFO: [XFORM 203-603] Inlining function 'OutputCache::setOutChannel' into 'ProcessingElement::processAll_channelOut' (src/fpgaAcc.cpp:251).
INFO: [XFORM 203-603] Inlining function 'OutputCache::getOutChannel' into 'OutputCache::accumulateChannel' (src/fpgaAcc.cpp:384).
INFO: [XFORM 203-603] Inlining function 'OutputCache::accumulateChannel' into 'ProcessingElement::processAll_channelOut' (src/fpgaAcc.cpp:253).
INFO: [XFORM 203-603] Inlining function 'MemoryController::writeBackOutputChannel' into 'convolution_3x3' (src/fpgaAcc.cpp:109).
INFO: [HLS 200-111] Finished Standard Transforms Time (s): cpu = 00:00:34 ; elapsed = 00:00:23 . Memory (MB): peak = 361.926 ; gain = 13.664 ; free physical = 341 ; free virtual = 32659
INFO: [HLS 200-10] Checking synthesizability ...
INFO: [XFORM 203-602] Inlining function 'ImageCache::writeNextChannelPixel_2_IBRAM' into 'convolution_3x3' (src/fpgaAcc.cpp:342->src/fpgaAcc.cpp:333->src/fpgaAcc.cpp:86) automatically.
INFO: [HLS 200-111] Finished Checking Synthesizability Time (s): cpu = 00:00:35 ; elapsed = 00:00:24 . Memory (MB): peak = 361.926 ; gain = 13.664 ; free physical = 338 ; free virtual = 32656
INFO: [XFORM 203-502] Unrolling all sub-loops inside loop 'L_CH_OUT' (src/fpgaAcc.cpp:240) in function 'ProcessingElement::processAll_channelOut' for pipelining.
INFO: [XFORM 203-501] Unrolling loop 'L_CH_OUT' (src/fpgaAcc.cpp:240) in function 'ProcessingElement::processAll_channelOut' partially with a factor of 8.
INFO: [XFORM 203-501] Unrolling loop 'Loop-1.1' (src/fpgaAcc.cpp:310) in function 'ProcessingElement::processAll_channelOut' completely.
INFO: [XFORM 203-501] Unrolling loop 'L_MACC_multiply' (src/fpgaAcc.cpp:190) in function 'ProcessingElement::processAll_channelOut' completely.
INFO: [XFORM 203-501] Unrolling loop 'L_MACC_accumulate' (src/fpgaAcc.cpp:195) in function 'ProcessingElement::processAll_channelOut' completely.
INFO: [XFORM 203-101] Partitioning array 'pixel_buffer' (src/fpgaAcc.cpp:228) in dimension 1 completely.
INFO: [XFORM 203-101] Partitioning array 'weights_local' (src/fpgaAcc.cpp:243) in dimension 1 completely.
INFO: [XFORM 203-101] Partitioning array 'WeightsCache::WBRAM' in dimension 1 completely.
INFO: [XFORM 203-101] Partitioning array 'multresult' (src/fpgaAcc.cpp:187) in dimension 1 completely.
INFO: [XFORM 203-101] Partitioning array 'OutputCache::OBRAM' in dimension 1 with a cyclic factor 8.
INFO: [XFORM 203-101] Partitioning array 'WeightsCache::WBRAM.0' in dimension 2 completely.
INFO: [XFORM 203-101] Partitioning array 'WeightsCache::WBRAM.1' in dimension 2 completely.
INFO: [XFORM 203-101] Partitioning array 'WeightsCache::WBRAM.2' in dimension 2 completely.
INFO: [XFORM 203-101] Partitioning array 'WeightsCache::WBRAM.3' in dimension 2 completely.
INFO: [XFORM 203-101] Partitioning array 'WeightsCache::WBRAM.4' in dimension 2 completely.
INFO: [XFORM 203-101] Partitioning array 'WeightsCache::WBRAM.5' in dimension 2 completely.
INFO: [XFORM 203-101] Partitioning array 'WeightsCache::WBRAM.6' in dimension 2 completely.
INFO: [XFORM 203-101] Partitioning array 'WeightsCache::WBRAM.7' in dimension 2 completely.
INFO: [XFORM 203-602] Inlining function 'ImageCache::writeNextChannelPixel_2_IBRAM' into 'convolution_3x3' (src/fpgaAcc.cpp:342->src/fpgaAcc.cpp:333->src/fpgaAcc.cpp:86) automatically.
INFO: [XFORM 203-622] Instantiating function 'ProcessingElement::processInputChannel'(src/fpgaAcc.cpp:221) to 'ProcessingElement::processInputChannel.0' at call site (src/fpgaAcc.cpp:103) by setting 'cur_ci' to 'cur_channel_in'.
INFO: [XFORM 203-721] Changing loop 'Loop_load_pixel_2_PE_row_loop_proc' (src/fpgaAcc.cpp:207) to a process function for dataflow in function 'ProcessingElement::processInputChannel.0'.
INFO: [XFORM 203-712] Applying dataflow to function 'ProcessingElement::processInputChannel.0' (src/fpgaAcc.cpp:224:1), detected/extracted 2 process function(s):
'ProcessingElement::processInputChannel.0_Loop_load_pixel_2_PE_row_loop_proc6'
'ProcessingElement::processAll_channelOut'.
INFO: [HLS 200-111] Finished Pre-synthesis Time (s): cpu = 00:00:38 ; elapsed = 00:00:27 . Memory (MB): peak = 489.633 ; gain = 141.371 ; free physical = 309 ; free virtual = 32630
WARNING: [XFORM 203-542] Cannot flatten a loop nest 'Loop-1.1' (src/fpgaAcc.cpp:282:18) in function 'convolution_3x3' :
the outer loop is not a perfect loop.
WARNING: [XFORM 203-542] Cannot flatten a loop nest 'Loop-1' (src/fpgaAcc.cpp:279:18) in function 'convolution_3x3' :
the outer loop is not a perfect loop.
WARNING: [XFORM 203-542] Cannot flatten a loop nest 'L_DRAM_PRELOADROW_X' (src/fpgaAcc.cpp:331:77) in function 'convolution_3x3' :
the outer loop is not a perfect loop.
WARNING: [XFORM 203-542] Cannot flatten a loop nest 'L_DRAM_PRELOADROW_X' (src/fpgaAcc.cpp:331:77) in function 'convolution_3x3' :
the outer loop is not a perfect loop.
WARNING: [XFORM 203-542] Cannot flatten a loop nest 'L_DRAM_PRELOADROW_X' (src/fpgaAcc.cpp:331:77) in function 'convolution_3x3' :
the outer loop is not a perfect loop.
WARNING: [XFORM 203-542] Cannot flatten a loop nest 'Loop-4.1' (src/fpgaAcc.cpp:93:3) in function 'convolution_3x3' :
the outer loop is not a perfect loop.
WARNING: [XFORM 203-542] Cannot flatten a loop nest 'row_loop' (src/fpgaAcc.cpp:91:85) in function 'convolution_3x3' :
more than one sub loop.
WARNING: [XFORM 203-631] Renaming function 'ProcessingElement::processInputChannel.0_Loop_load_pixel_2_PE_row_loop_proc6' to 'processInputChannel.' (src/fpgaAcc.cpp:207:3)
WARNING: [XFORM 203-631] Renaming function 'ProcessingElement::processInputChannel.0' to 'processInputChannel..1' (src/fpgaAcc.cpp:226:1)
WARNING: [XFORM 203-631] Renaming function 'ProcessingElement::processAll_channelOut' to 'processAll_channelOu' (src/fpgaAcc.cpp:192:50)
WARNING: [XFORM 203-631] Renaming function 'MemoryController::load_weight_2_reg' to 'load_weight_2_reg' (src/fpgaAcc.cpp:175)
WARNING: [XFORM 203-562] Loop 'L_CH_OUT' (src/fpgaAcc.cpp:240) in function 'processAll_channelOu' has unknown bound because it has multiple exiting blocks.
WARNING: [XFORM 203-713] Function 'processInputChannel..1' (src/fpgaAcc.cpp:226:1) failed dataflow checking: A dataflow region cannot be instantiated from with a pipelined loop (src/fpgaAcc.cpp:226:1). Ignoring pipeline directive to allow the dataflow directive to take precedence. This behavior can be disabled by using 'config_compile -disable_dataflow_pipeline_check'.
INFO: [HLS 200-111] Finished Architecture Synthesis Time (s): cpu = 00:00:40 ; elapsed = 00:00:30 . Memory (MB): peak = 553.633 ; gain = 205.371 ; free physical = 264 ; free virtual = 32586
INFO: [HLS 200-10] Starting hardware synthesis ...
INFO: [HLS 200-10] Synthesizing 'convolution_3x3' ...
WARNING: [SYN 201-103] Legalizing function name 'reg<float>' to 'reg_float_s'.
WARNING: [SYN 201-103] Legalizing function name 'processInputChannel.' to 'processInputChannel_s'.
WARNING: [SYN 201-103] Legalizing function name 'processInputChannel..1' to 'processInputChannel_1'.
WARNING: [SYN 201-303] Cannot apply functional unit assignment of 'MulnS' on 'weight_DRAM_ptr_offset1', which is not an operation.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-42] -- Implementing module 'reg_float_s'
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [SCHED 204-11] Starting scheduling ...
INFO: [SCHED 204-61] Pipelining function 'reg<float>'.
INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2.
INFO: [SCHED 204-11] Finished scheduling.
INFO: [HLS 200-111] Elapsed time: 29.84 seconds; current allocated memory: 133.651 MB.
INFO: [BIND 205-100] Starting micro-architecture generation ...
INFO: [BIND 205-101] Performing variable lifetime analysis.
INFO: [BIND 205-101] Exploring resource sharing.
INFO: [BIND 205-101] Binding ...
INFO: [BIND 205-100] Finished micro-architecture generation.
INFO: [HLS 200-111] Elapsed time: 0.03 seconds; current allocated memory: 133.712 MB.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-42] -- Implementing module 'load_weight_2_reg'
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [SCHED 204-11] Starting scheduling ...
INFO: [SCHED 204-61] Pipelining function 'load_weight_2_reg'.
INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 10.
INFO: [SCHED 204-11] Finished scheduling.
INFO: [HLS 200-111] Elapsed time: 0.06 seconds; current allocated memory: 133.903 MB.
INFO: [BIND 205-100] Starting micro-architecture generation ...
INFO: [BIND 205-101] Performing variable lifetime analysis.
INFO: [BIND 205-101] Exploring resource sharing.
INFO: [BIND 205-101] Binding ...
INFO: [BIND 205-100] Finished micro-architecture generation.
INFO: [HLS 200-111] Elapsed time: 0.07 seconds; current allocated memory: 133.998 MB.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-42] -- Implementing module 'processInputChannel_s'
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [SCHED 204-11] Starting scheduling ...
INFO: [SCHED 204-11] Finished scheduling.
INFO: [HLS 200-111] Elapsed time: 0.17 seconds; current allocated memory: 134.634 MB.
INFO: [BIND 205-100] Starting micro-architecture generation ...
INFO: [BIND 205-101] Performing variable lifetime analysis.
INFO: [BIND 205-101] Exploring resource sharing.
INFO: [BIND 205-101] Binding ...
INFO: [BIND 205-100] Finished micro-architecture generation.
INFO: [HLS 200-111] Elapsed time: 0.12 seconds; current allocated memory: 134.997 MB.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-42] -- Implementing module 'processAll_channelOu'
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [SCHED 204-11] Starting scheduling ...
INFO: [SCHED 204-61] Pipelining loop 'L_CH_OUT'.
INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 52.
INFO: [SCHED 204-11] Finished scheduling.
INFO: [HLS 200-111] Elapsed time: 2.25 seconds; current allocated memory: 137.424 MB.
INFO: [BIND 205-100] Starting micro-architecture generation ...
INFO: [BIND 205-101] Performing variable lifetime analysis.
INFO: [BIND 205-101] Exploring resource sharing.
INFO: [BIND 205-101] Binding ...
INFO: [BIND 205-100] Finished micro-architecture generation.
INFO: [HLS 200-111] Elapsed time: 1.71 seconds; current allocated memory: 141.035 MB.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-42] -- Implementing module 'processInputChannel_1'
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [SCHED 204-11] Starting scheduling ...
INFO: [SCHED 204-11] Finished scheduling.
INFO: [HLS 200-111] Elapsed time: 2.11 seconds; current allocated memory: 141.218 MB.
INFO: [BIND 205-100] Starting micro-architecture generation ...
INFO: [BIND 205-101] Performing variable lifetime analysis.
INFO: [BIND 205-101] Exploring resource sharing.
INFO: [BIND 205-101] Binding ...
INFO: [BIND 205-100] Finished micro-architecture generation.
INFO: [HLS 200-111] Elapsed time: 0.84 seconds; current allocated memory: 141.546 MB.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-42] -- Implementing module 'convolution_3x3'
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [SCHED 204-11] Starting scheduling ...
INFO: [SCHED 204-61] Pipelining loop 'Loop 1.1.1'.
INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 12.
INFO: [SCHED 204-61] Pipelining loop 'L_PRELOAD_PIXEL_FROM_DRAM'.
INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 14.
INFO: [SCHED 204-61] Pipelining loop 'L_PRELOAD_PIXEL_FROM_DRAM'.
INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 14.
INFO: [SCHED 204-11] Finished scheduling.
INFO: [HLS 200-111] Elapsed time: 1.75 seconds; current allocated memory: 144.533 MB.
INFO: [BIND 205-100] Starting micro-architecture generation ...
INFO: [BIND 205-101] Performing variable lifetime analysis.
INFO: [BIND 205-101] Exploring resource sharing.
INFO: [BIND 205-101] Binding ...
INFO: [BIND 205-100] Finished micro-architecture generation.
INFO: [HLS 200-111] Elapsed time: 2.05 seconds; current allocated memory: 147.460 MB.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-10] -- Generating RTL for module 'reg_float_s'
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [RTGEN 206-100] Finished creating RTL model for 'reg_float_s'.
INFO: [HLS 200-111] Elapsed time: 1.94 seconds; current allocated memory: 147.725 MB.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-10] -- Generating RTL for module 'load_weight_2_reg'
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [RTGEN 206-100] Finished creating RTL model for 'load_weight_2_reg'.
INFO: [HLS 200-111] Elapsed time: 0.03 seconds; current allocated memory: 148.372 MB.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-10] -- Generating RTL for module 'processInputChannel_s'
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_mul_32s_32s_32_3_1' to 'convolution_3x3_mbkb' due to the length limit 20
INFO: [RTGEN 206-100] Generating core module 'convolution_3x3_mbkb': 2 instance(s).
INFO: [RTGEN 206-100] Finished creating RTL model for 'processInputChannel_s'.
INFO: [HLS 200-111] Elapsed time: 0.17 seconds; current allocated memory: 149.415 MB.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-10] -- Generating RTL for module 'processAll_channelOu'
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_fadd_32ns_32ns_32_4_full_dsp_1' to 'convolution_3x3_fcud' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_fmul_32ns_32ns_32_3_max_dsp_1' to 'convolution_3x3_fdEe' due to the length limit 20
INFO: [RTGEN 206-100] Generating core module 'convolution_3x3_fcud': 80 instance(s).
INFO: [RTGEN 206-100] Generating core module 'convolution_3x3_fdEe': 72 instance(s).
INFO: [RTGEN 206-100] Finished creating RTL model for 'processAll_channelOu'.
INFO: [HLS 200-111] Elapsed time: 0.82 seconds; current allocated memory: 158.632 MB.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-10] -- Generating RTL for module 'processInputChannel_1'
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [RTGEN 206-100] Finished creating RTL model for 'processInputChannel_1'.
INFO: [HLS 200-111] Elapsed time: 4.18 seconds; current allocated memory: 169.745 MB.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-10] -- Generating RTL for module 'convolution_3x3'
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [RTGEN 206-500] Setting interface mode on port 'convolution_3x3/memorybus' to 'm_axi'.
INFO: [RTGEN 206-500] Setting interface mode on port 'convolution_3x3/inHight' to 's_axilite & ap_none' (register).
INFO: [RTGEN 206-500] Setting interface mode on port 'convolution_3x3/inWidth' to 's_axilite & ap_none' (register).
INFO: [RTGEN 206-500] Setting interface mode on port 'convolution_3x3/inChanNum' to 's_axilite & ap_none' (register).
INFO: [RTGEN 206-500] Setting interface mode on port 'convolution_3x3/outHight' to 's_axilite & ap_none' (register).
INFO: [RTGEN 206-500] Setting interface mode on port 'convolution_3x3/outWidth' to 's_axilite & ap_none' (register).
INFO: [RTGEN 206-500] Setting interface mode on port 'convolution_3x3/OutChanNum' to 's_axilite & ap_none' (register).
INFO: [RTGEN 206-500] Setting interface mode on port 'convolution_3x3/stride' to 's_axilite & ap_none' (register).
INFO: [RTGEN 206-500] Setting interface mode on port 'convolution_3x3/weight_ptr' to 's_axilite & ap_none'.
INFO: [RTGEN 206-500] Setting interface mode on port 'convolution_3x3/input_ptr' to 's_axilite & ap_none'.
INFO: [RTGEN 206-500] Setting interface mode on port 'convolution_3x3/output_ptr' to 's_axilite & ap_none'.
INFO: [RTGEN 206-500] Setting interface mode on function 'convolution_3x3' to 'ap_ctrl_hs'.
WARNING: [RTGEN 206-101] Register 'MemoryController_ou_5' is power-on initialization.
WARNING: [RTGEN 206-101] Global scalar 'MemoryController_ou_5' will not be exposed as RTL port.
WARNING: [RTGEN 206-101] Register 'MemoryController_ou' is power-on initialization.
WARNING: [RTGEN 206-101] Global scalar 'MemoryController_ou' will not be exposed as RTL port.
WARNING: [RTGEN 206-101] Register 'MemoryController_ou_3' is power-on initialization.
WARNING: [RTGEN 206-101] Global scalar 'MemoryController_ou_3' will not be exposed as RTL port.
WARNING: [RTGEN 206-101] Register 'MemoryController_ou_4' is power-on initialization.
WARNING: [RTGEN 206-101] Global scalar 'MemoryController_ou_4' will not be exposed as RTL port.
WARNING: [RTGEN 206-101] Register 'MemoryController_in' is power-on initialization.
WARNING: [RTGEN 206-101] Global scalar 'MemoryController_in' will not be exposed as RTL port.
WARNING: [RTGEN 206-101] Register 'MemoryController_st' is power-on initialization.
WARNING: [RTGEN 206-101] Global scalar 'MemoryController_st' will not be exposed as RTL port.
WARNING: [RTGEN 206-101] Register 'MemoryController_in_1' is power-on initialization.
WARNING: [RTGEN 206-101] Global scalar 'MemoryController_in_1' will not be exposed as RTL port.
WARNING: [RTGEN 206-101] Register 'MemoryController_cu_1' is power-on initialization.
WARNING: [RTGEN 206-101] Global scalar 'MemoryController_cu_1' will not be exposed as RTL port.
WARNING: [RTGEN 206-101] Register 'MemoryController_cu' is power-on initialization.
WARNING: [RTGEN 206-101] Global scalar 'MemoryController_cu' will not be exposed as RTL port.
WARNING: [RTGEN 206-101] Global scalar 'ImageCache_in_heigh' will not be exposed as RTL port.
WARNING: [RTGEN 206-101] Register 'ImageCache_in_width' is power-on initialization.
WARNING: [RTGEN 206-101] Global scalar 'ImageCache_in_width' will not be exposed as RTL port.
WARNING: [RTGEN 206-101] Register 'ImageCache_in_Chann_1' is power-on initialization.
WARNING: [RTGEN 206-101] Global scalar 'ImageCache_in_Chann_1' will not be exposed as RTL port.
WARNING: [RTGEN 206-101] Global scalar 'ImageCache_in_Chann' will not be exposed as RTL port.
WARNING: [RTGEN 206-101] Register 'ImageCache_MAX_IBRA' is power-on initialization.
WARNING: [RTGEN 206-101] Global scalar 'ImageCache_MAX_IBRA' will not be exposed as RTL port.
WARNING: [RTGEN 206-101] Register 'ImageCache_cur_IBRA' is power-on initialization.
WARNING: [RTGEN 206-101] Global scalar 'ImageCache_cur_IBRA' will not be exposed as RTL port.
WARNING: [RTGEN 206-101] Register 'WeightsCache_outCha' is power-on initialization.
WARNING: [RTGEN 206-101] Global scalar 'WeightsCache_outCha' will not be exposed as RTL port.
WARNING: [RTGEN 206-101] Register 'WeightsCache_inChan' is power-on initialization.
WARNING: [RTGEN 206-101] Global scalar 'WeightsCache_inChan' will not be exposed as RTL port.
WARNING: [RTGEN 206-101] Register 'MemoryController_pi' is power-on initialization.
WARNING: [RTGEN 206-101] Global scalar 'MemoryController_pi' will not be exposed as RTL port.
WARNING: [RTGEN 206-101] Register 'MemoryController_lo' is power-on initialization.
WARNING: [RTGEN 206-101] Global scalar 'MemoryController_lo' will not be exposed as RTL port.
WARNING: [RTGEN 206-101] Global array 'ImageCache_IBRAM' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_ImageCache_IBRAM' to 'convolution_3x3_IeOg' due to the length limit 20
WARNING: [RTGEN 206-101] Register 'MemoryController_pe' is power-on initialization.
WARNING: [RTGEN 206-101] Global scalar 'MemoryController_pe' will not be exposed as RTL port.
WARNING: [RTGEN 206-101] Global array 'OBRAM_0' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_OBRAM_0' to 'convolution_3x3_OfYi' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_0_0' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_0_0' to 'convolution_3x3_Wg8j' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_0_1' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_0_1' to 'convolution_3x3_Whbi' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_0_2' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_0_2' to 'convolution_3x3_Wibs' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_0_3' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_0_3' to 'convolution_3x3_WjbC' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_0_4' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_0_4' to 'convolution_3x3_WkbM' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_0_5' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_0_5' to 'convolution_3x3_WlbW' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_0_6' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_0_6' to 'convolution_3x3_Wmb6' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_0_7' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_0_7' to 'convolution_3x3_Wncg' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_0_8' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_0_8' to 'convolution_3x3_Wocq' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'OBRAM_1' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_OBRAM_1' to 'convolution_3x3_OpcA' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_1_0' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_1_0' to 'convolution_3x3_WqcK' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_1_1' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_1_1' to 'convolution_3x3_WrcU' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_1_2' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_1_2' to 'convolution_3x3_Wsc4' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_1_3' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_1_3' to 'convolution_3x3_Wtde' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_1_4' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_1_4' to 'convolution_3x3_Wudo' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_1_5' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_1_5' to 'convolution_3x3_Wvdy' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_1_6' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_1_6' to 'convolution_3x3_WwdI' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_1_7' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_1_7' to 'convolution_3x3_WxdS' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_1_8' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_1_8' to 'convolution_3x3_Wyd2' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'OBRAM_2' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_OBRAM_2' to 'convolution_3x3_Ozec' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_2_0' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_2_0' to 'convolution_3x3_WAem' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_2_1' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_2_1' to 'convolution_3x3_WBew' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_2_2' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_2_2' to 'convolution_3x3_WCeG' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_2_3' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_2_3' to 'convolution_3x3_WDeQ' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_2_4' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_2_4' to 'convolution_3x3_WEe0' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_2_5' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_2_5' to 'convolution_3x3_WFfa' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_2_6' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_2_6' to 'convolution_3x3_WGfk' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_2_7' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_2_7' to 'convolution_3x3_WHfu' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_2_8' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_2_8' to 'convolution_3x3_WIfE' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'OBRAM_3' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_OBRAM_3' to 'convolution_3x3_OJfO' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_3_0' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_3_0' to 'convolution_3x3_WKfY' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_3_1' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_3_1' to 'convolution_3x3_WLf8' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_3_2' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_3_2' to 'convolution_3x3_WMgi' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_3_3' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_3_3' to 'convolution_3x3_WNgs' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_3_4' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_3_4' to 'convolution_3x3_WOgC' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_3_5' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_3_5' to 'convolution_3x3_WPgM' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_3_6' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_3_6' to 'convolution_3x3_WQgW' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_3_7' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_3_7' to 'convolution_3x3_WRg6' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_3_8' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_3_8' to 'convolution_3x3_WShg' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'OBRAM_4' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_OBRAM_4' to 'convolution_3x3_OThq' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_4_0' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_4_0' to 'convolution_3x3_WUhA' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_4_1' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_4_1' to 'convolution_3x3_WVhK' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_4_2' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_4_2' to 'convolution_3x3_WWhU' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_4_3' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_4_3' to 'convolution_3x3_WXh4' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_4_4' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_4_4' to 'convolution_3x3_WYie' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_4_5' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_4_5' to 'convolution_3x3_WZio' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_4_6' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_4_6' to 'convolution_3x3_W0iy' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_4_7' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_4_7' to 'convolution_3x3_W1iI' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_4_8' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_4_8' to 'convolution_3x3_W2iS' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'OBRAM_5' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_OBRAM_5' to 'convolution_3x3_O3i2' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_5_0' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_5_0' to 'convolution_3x3_W4jc' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_5_1' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_5_1' to 'convolution_3x3_W5jm' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_5_2' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_5_2' to 'convolution_3x3_W6jw' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_5_3' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_5_3' to 'convolution_3x3_W7jG' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_5_4' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_5_4' to 'convolution_3x3_W8jQ' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_5_5' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_5_5' to 'convolution_3x3_W9j0' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_5_6' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_5_6' to 'convolution_3x3_Wbak' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_5_7' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_5_7' to 'convolution_3x3_Wbbk' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_5_8' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_5_8' to 'convolution_3x3_Wbck' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'OBRAM_6' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_OBRAM_6' to 'convolution_3x3_Obdk' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_6_0' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_6_0' to 'convolution_3x3_Wbek' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_6_1' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_6_1' to 'convolution_3x3_Wbfk' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_6_2' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_6_2' to 'convolution_3x3_Wbgk' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_6_3' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_6_3' to 'convolution_3x3_Wbhl' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_6_4' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_6_4' to 'convolution_3x3_Wbil' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_6_5' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_6_5' to 'convolution_3x3_Wbjl' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_6_6' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_6_6' to 'convolution_3x3_Wbkl' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_6_7' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_6_7' to 'convolution_3x3_Wbll' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_6_8' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_6_8' to 'convolution_3x3_Wbml' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'OBRAM_7' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_OBRAM_7' to 'convolution_3x3_Obnm' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_7_0' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_7_0' to 'convolution_3x3_Wbom' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_7_1' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_7_1' to 'convolution_3x3_Wbpm' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_7_2' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_7_2' to 'convolution_3x3_Wbqm' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_7_3' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_7_3' to 'convolution_3x3_Wbrm' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_7_4' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_7_4' to 'convolution_3x3_Wbsm' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_7_5' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_7_5' to 'convolution_3x3_Wbtn' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_7_6' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_7_6' to 'convolution_3x3_Wbun' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_7_7' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_7_7' to 'convolution_3x3_Wbvn' due to the length limit 20
WARNING: [RTGEN 206-101] Global array 'WBRAM_7_8' will not be exposed as RTL port.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_WBRAM_7_8' to 'convolution_3x3_Wbwn' due to the length limit 20
INFO: [RTGEN 206-100] Bundling port 'weight_ptr', 'input_ptr' and 'output_ptr' to AXI-Lite port AXILiteS.
INFO: [RTGEN 206-100] Bundling port 'inHight', 'inWidth', 'inChanNum', 'outHight', 'outWidth', 'OutChanNum' and 'stride' to AXI-Lite port axilite.
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_mul_32s_5ns_32_3_1' to 'convolution_3x3_mbxn' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'convolution_3x3_mux_83_32_1_1' to 'convolution_3x3_mbyn' due to the length limit 20
INFO: [RTGEN 206-100] Generating core module 'convolution_3x3_mbkb': 13 instance(s).
INFO: [RTGEN 206-100] Generating core module 'convolution_3x3_mbxn': 1 instance(s).
INFO: [RTGEN 206-100] Generating core module 'convolution_3x3_mbyn': 1 instance(s).
INFO: [RTGEN 206-100] Finished creating RTL model for 'convolution_3x3'.
INFO: [HLS 200-111] Elapsed time: 4.79 seconds; current allocated memory: 180.173 MB.
INFO: [RTMG 210-282] Generating pipelined core: 'convolution_3x3_mbkb_MulnS_0'
INFO: [RTMG 210-285] Implementing FIFO 'fifo_w32_d2_A' using Shift Registers.
INFO: [RTMG 210-285] Implementing FIFO 'fifo_w32_d2_A' using Shift Registers.
INFO: [RTMG 210-285] Implementing FIFO 'fifo_w32_d2_A' using Shift Registers.
INFO: [RTMG 210-285] Implementing FIFO 'fifo_w32_d2_A' using Shift Registers.
INFO: [RTMG 210-285] Implementing FIFO 'fifo_w32_d2_A' using Shift Registers.
INFO: [RTMG 210-285] Implementing FIFO 'fifo_w32_d2_A' using Shift Registers.
INFO: [RTMG 210-285] Implementing FIFO 'fifo_w32_d2_A' using Shift Registers.
INFO: [RTMG 210-285] Implementing FIFO 'fifo_w32_d2_A' using Shift Registers.
INFO: [RTMG 210-285] Implementing FIFO 'fifo_w32_d2_A' using Shift Registers.
INFO: [RTMG 210-282] Generating pipelined core: 'convolution_3x3_mbxn_MulnS_1'
INFO: [RTMG 210-278] Implementing memory 'convolution_3x3_IeOg_ram (RAM_S2P_BRAM)' using block RAMs with power-on initialization.
INFO: [RTMG 210-278] Implementing memory 'convolution_3x3_OfYi_ram (RAM_T2P_BRAM)' using block RAMs with power-on initialization.
INFO: [RTMG 210-278] Implementing memory 'convolution_3x3_Wg8j_ram (RAM_S2P_BRAM)' using block RAMs with power-on initialization.
INFO: [HLS 200-111] Finished generating all RTL models Time (s): cpu = 00:01:03 ; elapsed = 00:00:59 . Memory (MB): peak = 553.633 ; gain = 205.371 ; free physical = 170 ; free virtual = 32518
INFO: [SYSC 207-301] Generating SystemC RTL for convolution_3x3.
INFO: [VHDL 208-304] Generating VHDL RTL for convolution_3x3.
INFO: [VLOG 209-307] Generating Verilog RTL for convolution_3x3.
INFO: [HLS 200-112] Total elapsed time: 59.2 seconds; peak allocated memory: 180.173 MB.
Finished C synthesis.
2.2 N_PE=4
N_PE改为4之后，相应的 extern float WBRAM[N_PE][MAX_2D_FILTERS_PER_PE][9];
MAX_2D_FILTERS_PER_PE要从512改为1024
资源与时钟周期与上面一模一样。但是BRAM增加了一倍，基本说明WBRAM的使用增加了一倍。
三、最终IPcore占用的资源
7z020
7020平台上。为尽快输出IPcore，暂时不加TRIPCOUNT指令输出时钟周期，时钟周期后续优化。暂时第一时间将IPcore实现在FPGA之上。
| Estimated clock | BRAM | DSP48E | FF | LUT | |
| 占用百分比 | 8.75ns | 35% | 209% | 42% | 122% |
| 数量 | 100 | 461 | 45105 | 64959 | |
| zynqNet对比（7045平台） | 8.75ns | 996 | 771 | 105780 | 158471 |
7z035ffg676-2
四、输出IPcore为RTL
Starting export RTL ...
/mnt/workspace/Xilinx/Vivado/2017.4/bin/vivado_hls /home/osrc/Desktop/document/conv_Core/HLS_Conv/conv3x3_IPcore/7035IPcore/export.tcl
INFO: [HLS 200-10] Running '/mnt/workspace/Xilinx/Vivado/2017.4/bin/unwrapped/lnx64.o/vivado_hls'
INFO: [HLS 200-10] For user 'osrc' on host 'osrc-virtual-machine' (Linux_x86_64 version 4.13.0-32-generic) on Thu Dec 13 10:23:29 CST 2018
INFO: [HLS 200-10] On os Ubuntu 16.04.3 LTS
INFO: [HLS 200-10] In directory '/home/osrc/Desktop/document/conv_Core/HLS_Conv'
INFO: [HLS 200-10] Opening project '/home/osrc/Desktop/document/conv_Core/HLS_Conv/conv3x3_IPcore'.
INFO: [HLS 200-10] Opening solution '/home/osrc/Desktop/document/conv_Core/HLS_Conv/conv3x3_IPcore/7035IPcore'.
INFO: [SYN 201-201] Setting up clock 'default' with a period of 10ns.
INFO: [HLS 200-10] Setting target device to 'xc7z035ffg676-2'
INFO: [IMPL 213-8] Exporting RTL as a Vivado IP.
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