Verilog HDL语言设计实现过程赋值+译码器

• 完成课本例题6.11、6.12，进行综合和仿真（功能仿真），查看综合和仿真结果，整理入实验报告。

6.11

module shiyan21(in,clk,out1,out2);

input clk,in;

output out1,out2;

reg out1,out2;

always @(posedge clk)

begin

out1<=in;

out2<=out1;

end

endmodule

`timescale 1ns/1ns

 

module test();

reg in,clk;

wire out1,out2;

shiyan21 U1(in,clk,out1,out2);

always #10 clk=~clk;

initial

begin clk =0;in=0;

#10 in=1;

#20 in=0;

#10 in