fclk if总线_[DM3730]请教关于DM3730中GPMC总线时钟FCLK频率更改问题

如题，本人现在在使用GPMC与FPGA通讯，现在问题是频率有些高，想降低到50M左右，现在FCLK的频率是200M。

参考http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/716/t/282404.aspx做修改，发现

clk_set_rate(clkp, rate)函数中的rate值并不是刻意随便更改的，目前只能更改为200000000，源程序中的值为400000000.

想请教一下论坛的前辈，是不是我修改的地方不对，还是其他原因，为什么频率没法改呢？

我修改的文档为：

linux/arch/arm/mach-omap2/Clock34xx.c

下面为该文档中我修改的函数，红色部分为我修改的地方。

int __init omap2_clk_set_freq(void)

{

struct clk *osc_sys_ck, *dpll1_ck, *arm_fck, *core_ck;

struct clk *dpll2_ck, *iva2_ck, *dpll3_m2_ck;

unsigned long osc_sys_rate;

unsigned long dsprate, l3rate;

short err = 0 ;

int l3div;

/*

* Check if any processing is required.

*/

if ((vdd1_opp == 0) && (vdd2_opp == 0))

return 0;

if (WARN((vdd1_opp == 0), "VDD1 OPP is not set.\n"))

err = 1;

if (WARN((vdd2_opp == 0), "VDD2 OPP is not set.\n"))

err = 1;

/*

* Attempt to get the required clocks

*/

dpll1_ck = clk_get(NULL, "dpll1_ck");

if (WARN(IS_ERR(dpll1_ck), "Failed to get dpll1_ck.\n"))

err = 1;

arm_fck = clk_get(NULL, "arm_fck");

if (WARN(IS_ERR(arm_fck), "Failed to get arm_fck.\n"))

err = 1;

core_ck = clk_get(NULL, "core_ck");

if (WARN(IS_ERR(core_ck), "Failed to get core_ck.\n"))

err = 1;

osc_sys_ck = clk_get(NULL, "osc_sys_ck");

if (WARN(IS_ERR(osc_sys_ck), "Failed to get osc_sys_ck.\n"))

err = 1;

dpll2_ck = clk_get(NULL, "dpll2_ck");

if (WARN(IS_ERR("dpll2_ck"), "Failed to get dpll2_ck.\n"))

err = 1;

iva2_ck = clk_get(NULL, "iva2_ck");

if (WARN(IS_ERR("iva2_ck"), "Failed to get iva2_ck.\n"))

err = 1;

dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck");

if (WARN(IS_ERR("dpll3_m2_ck"), "Failed to get dpll3_m2_ck.\n"))

err = 1;

if (err)

return -ENOENT;

/*

* Set MPU frequency

*/

mpurate = mpu_opps [vdd1_opp].rate;

if (clk_set_rate(dpll1_ck, mpurate))

pr_err("Unable to set MPU frequency (%u)\n", mpurate);

/*

* Set DSP frequency

*/

if (omap3_has_iva()) {

omap2_clk_iva_init_to_idle();

dsprate = dsp_opps [vdd1_opp].rate;

if (clk_set_rate(dpll2_ck, dsprate))

pr_err("Unable to set DSP frequency (%lu)\n", dsprate);

}

/*

* Set L3 frequency

*/

l3div  = cm_read_mod_reg(CORE_MOD, CM_CLKSEL) &

OMAP3430_CLKSEL_L3_MASK;

l3rate = l3_opps[vdd2_opp].rate * l3div;

if (clk_set_rate(dpll3_m2_ck, l3rate))

pr_err("Unable to set L3 frequency (%lu)\n", l3rate);

/*

* Re-calculate the clocks

*/

recalculate_root_clocks();

osc_sys_rate = clk_get_rate(osc_sys_ck);

pr_info("Switched to new clocking rate (Crystal/Core/MPU): "

"%ld.%01ld/%ld/%ld MHz\n",

(osc_sys_rate / 1000000),

((osc_sys_rate / 100000) % 10),

(clk_get_rate(core_ck) / 1000000),

(clk_get_rate(arm_fck) / 1000000));

if (omap3_has_iva()) {

pr_info("IVA2 clocking rate: %ld MHz\n",

(clk_get_rate(iva2_ck) / 1000000)) ;

}

calibrate_delay();

return 0;

}