vfifo控制mig_AXI_MIG ISE生成的AXI接口的MIG，内存控制器，语言：verilog VHDL-FPGA- 238万源代码下载- www.pudn.com...

文件名称: AXI_MIG下载

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开发工具: VHDL

文件大小: 730 KB

上传时间: 2013-04-09

下载次数: 15

提 供 者: 王小玲

详细说明：ISE生成的AXI接口的MIG，内存控制器，语言：verilog-ISE generated the AXI interface MIG, memory controller, language: verilog

文件列表(点击判断是否您需要的文件，如果是垃圾请在下面评价投诉):

AXI_MIG\AXI_MIG.csv

.......\datasheet.txt

.......\.ocs\phy_only_support_readme.txt

.......\....\ug586_7Series_MIS.pdf

.......\example_design\log.txt

.......\..............\par\create_ise.bat

.......\..............\...\ddr_ila_basic_cg.xco

.......\..............\...\ddr_ila_rdpath_cg.xco

.......\..............\...\ddr_ila_wrpath_cg.xco

.......\..............\...\ddr_vio_sync_async_out72_cg.xco

.......\..............\...\example_top.cdc

.......\..............\...\example_top.cpj

.......\..............\...\example_top.ucf

.......\..............\...\example_top.xdc

.......\..............\...\icon4_cg.xco

.......\..............\...\ise_flow.bat

.......\..............\...\makeproj.bat

.......\..............\...\readme.txt

.......\..............\...\rem_files.bat

.......\..............\...\rem_files.tcl

.......\..............\...\set_ise_prop.tcl

.......\..............\...\vivado.tcl

.......\..............\...\vivado_gui.tcl

.......\..............\...\xst_options.txt

.......\..............\rtl\example_top.v

.......\..............\...\traffic_gen\axi4_tg.v

.......\..............\...\...........\axi4_wrapper.v

.......\..............\...\...........\cmd_prbs_gen_axi.v

.......\..............\...\...........\data_gen_chk.v

.......\..............\...\...........\tg.v

.......\..............\sim\ddr3_model.v

.......\..............\...\ddr3_model_parameters.vh

.......\..............\...\isim_files.prj

.......\..............\...\isim_options.tcl

.......\..............\...\isim_run.bat

.......\..............\...\readme.txt

.......\..............\...\sim.do

.......\..............\...\sim_tb_top.v

.......\..............\...\wiredly.v

.......\..............\...\xsim_files.prj

.......\..............\...\xsim_options.tcl

.......\..............\...\xsim_run.bat

.......\..............\.ynth\example_top.lso

.......\..............\.....\example_top.prj

.......\mig.prj

.......\user_design\constraints\AXI_MIG.ucf

.......\...........\...........\AXI_MIG.xdc

.......\...........\log.txt

.......\...........\rtl\axi\axi_ctrl_addr_decode.v

.......\...........\...\...\axi_ctrl_read.v

.......\...........\...\...\axi_ctrl_reg.v

.......\...........\...\...\axi_ctrl_reg_bank.v

.......\...........\...\...\axi_ctrl_top.v

.......\...........\...\...\axi_ctrl_write.v

.......\...........\...\...\axi_mc.v

.......\...........\...\...\axi_mc_ar_channel.v

.......\...........\...\...\axi_mc_aw_channel.v

.......\...........\...\...\axi_mc_b_channel.v

.......\...........\...\...\axi_mc_cmd_arbiter.v

.......\...........\...\...\axi_mc_cmd_fsm.v

.......\...........\...\...\axi_mc_cmd_translator.v

.......\...........\...\...\axi_mc_incr_cmd.v

.......\...........\...\...\axi_mc_r_channel.v

.......\...........\...\...\axi_mc_simple_fifo.v

.......\...........\...\...\axi_mc_wrap_cmd.v

.......\...........\...\...\axi_mc_wr_cmd_fsm.v

.......\...........\...\...\axi_mc_w_channel.v

.......\...........\...\...\ddr_axic_register_slice.v

.......\...........\...\...\ddr_axi_register_slice.v

.......\...........\...\...\ddr_axi_upsizer.v

.......\...........\...\...\ddr_a_upsizer.v

.......\...........\...\...\ddr_carry_and.v

.......\...........\...\...\ddr_carry_latch_and.v

.......\...........\...\...\ddr_carry_latch_or.v

.......\...........\...\...\ddr_carry_or.v

.......\...........\...\...\ddr_command_fifo.v

.......\...........\...\...\ddr_comparator.v

.......\...........\...\...\ddr_comparator_sel.v

.......\...........\...\...\ddr_comparator_sel_static.v

.......\...........\...\...\ddr_r_upsizer.v

.......\...........\...\...\ddr_w_upsizer.v

.......\...........\...\AXI_MIG.v

.......\...........\...\clocking\clk_ibuf.v

.......\...........\...\........\infrastructure.v

.......\...........\...\........\iodelay_ctrl.v

.......\...........\...\.ontroller\arb_mux.v

.......\...........\...\..........\arb_row_col.v

.......\...........\...\..........\arb_select.v

.......\...........\...\..........\bank_cntrl.v

.......\...........\...\..........\bank_common.v

.......\...........\...\..........\bank_compare.v

.......\...........\...\..........\bank_mach.v

.......\...........\...\..........\bank_queue.v

.......\...........\...\..........\bank_state.v

.......\...........\...\..........\col_mach.v

.......\...........\...\..........\mc.v

.......\...........\...\..........\rank_cntrl.v

.......\...........\...\..........\rank_common.v

.......\...........\...\..........\rank_mach.v

.......\...........\...\..........\round_robin_arb.v

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