I try to design a bch code as a shift register, so I have this schematic:
(clickable)
And I made a VHDL code in Altera Quartus to design this shift register with loops, the compilation works but it doesn't make the expected result during the simulation in ModelSim (no output). It may have some errors in my code:
-- Library declaration
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_unsigned.ALL;
-- Entity declaration
ENTITY bchcode_implementation_top IS
PORT(clk : IN std_logic;
Q : OUT std_logic_vector(7 downto 0));
END bchcode_implementation_top;
-- Architecture declaration
ARCHITECTURE arch_bchcode_implementation_top OF bchcode_implementation_top IS
SIGNAL M: std_logic_vector(7 d