重温FPGA之两串行数据输入比较器 verilog实现

1.题目

2.源码 

// *********************************************************************************
// Project Name : serial_data_comparison
// Email        : 2972880695@qq.com
// Website      : https://home.cnblogs.com/u/hqz68/
// Create Time  : 2019/12/13 
// File Name    : serial_data_comparison.v
// Module Name  : serial_data_comparison
// Abstract     :
// editor		: sublime text 3
// *********************************************************************************
// Modification History:
// Date         By              Version                 Change Description
// -----------------------------------------------------------------------
// 2019/12/13    宏强子           1.0                     Original
//  
// *********************************************************************************
`timescale      1ns/1ns	
module serial_data_comparison (
	//system signals
	input					sclk			, 
	input					s_rst_n			,
	//input
	input					a				,
	input					b				,
	input					start			,
	//output
	output	reg	[1:0]		sout
);

//========================================================================\
// =========== Define Parameter and Internal signals =========== 
//========================================================================/
localparam		Small 	= 2'b01;
localparam		Equal 	= 2'b10;
localparam		Big 	= 2'b11;

reg	[3:0]		bit_cnt		;
reg				valid_flag	;

reg [7:0]		a_byte		;
reg [7:0]		b_byte		;

reg				rx_end		;
//=============================================================================
//****************************     Main Code    *******************************
//=============================================================================

//产生数据接收有效标志
always @ (posedge sclk or negedge s_rst_n) begin
	if(s_rst_n == 1'b0)
		valid_flag <= 1'b0;
	else if (start == 1'b1)
 		valid_flag <= 1'b1;
 	else if (bit_cnt == 4'd8)
 		valid_flag <=1'b0;
	else	
        valid_flag <= valid_flag;
end

//位计数器
always @ (posedge sclk or negedge s_rst_n) begin
	if(s_rst_n == 1'b0)
		bit_cnt <= 4'd0;
	else if (valid_flag == 1'b1)
		bit_cnt <= bit_cnt + 1'b1;
	else	
        bit_cnt <= 4'd0;
end

//串行数据接收
always @ (posedge sclk or negedge s_rst_n) begin
	if(s_rst_n == 1'b0) begin
		a_byte <= 8'd0;
		b_byte <= 8'd0;
	end
	else if (valid_flag == 1'b1) begin 
		a_byte <= {a,a_byte[7:1]};
		b_byte <= {b,b_byte[7:1]};	
	end        
	else begin
		a_byte <= a_byte;
		b_byte <= b_byte;		
	end      
end

//接收数据完成标志
always @ (posedge sclk or negedge s_rst_n) begin
	if(s_rst_n == 1'b0)
		rx_end <= 1'b0;
	else if (bit_cnt == 4'd8)
	    rx_end <= 1'b1;    
	else	
		rx_end <= 1'b0;       
end

//比较大小
always @ (posedge sclk or negedge s_rst_n) begin
	if(s_rst_n == 1'b0)
		sout <= 2'd0;
	else if (rx_end == 1'b1 & (a_byte < b_byte))
		sout <= Small; 
	else if (rx_end == 1'b1 & (a_byte == b_byte))
		sout <= Equal; 	
	else if (rx_end == 1'b1 & (a_byte > b_byte))
		sout <= Big; 	        
	else	
        sout <= 2'd0;
end

endmodule

3.测试平台

这次仿真用到task语句功能，生成串行数据

`timescale      1ns/1ns
module tb_sim();
reg				sclk		;
reg				s_rst_n		;
reg				a			;
reg				b			;
reg				start		;
wire	[1:0]	sout		;

initial	begin
	sclk = 1;
	s_rst_n = 0;
	start = 0;
	a = 1'b1;
	b = 1'b1;
	#50
	s_rst_n =1;

	#100
	start = 1;
	#50
	start = 0;
	tx_bit(8'd100,8'd100);
end

always #25	sclk = ~sclk;

task	tx_bit(
	input	[7:0]	data_a,
	input	[7:0]	data_b
	);
	integer i;
	for (i = 0; i < 8; i = i + 1)
	    begin
	       case (i) 
	            0:begin
	            	a <= data_a[0];
					b <= data_b[0];	
	            end        
	            1:begin
	            	a <= data_a[1];
					b <= data_b[1];	
	            end 
	            2:begin
	            	a <= data_a[2];
					b <= data_b[2];	
	            end 
	            3:begin
	            	a <= data_a[3];
					b <= data_b[3];	
	            end 
	            4:begin
	            	a <= data_a[4];
					b <= data_b[4];	
	            end 
	            5:begin
	            	a <= data_a[5];
					b <= data_b[5];	
	            end 
	            6:begin
	            	a <= data_a[6];
					b <= data_b[6];	
	            end
	            7:begin
	            	a <= data_a[7];
					b <= data_b[7];	
	            end  
	            default:begin
	            	a <= 1'b1;
					b <= 1'b1;	
	            end 
	        endcase
	        #50; 
	    end
endtask

 serial_data_comparison 	serial_data_inst(
	//system signals
	.sclk				(sclk		), 
	.s_rst_n			(s_rst_n	),
	//input
	.a					(a			),
	.b					(b			),
	.start				(start		),
	//output
	.sout				(sout		)
);

endmodule

4.仿真波形

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