ARM Generic Timer

• 了解 ARM Generic Timer

1.Introduction

  The Generic Timer in the Armv8-A can schedule events and trigger interrupts based on an incrementing counter value. It provides:

• Generation of timer events as interrupt outputs.
• Generation of event streams.

1.1.The Generic Timer

• Provides a system counter, that measures the passing of time in real-time.
• Supports virtual counters that measure the passing of virtual-time. That is, a virtual counter can measure the passing of time on a particular virtual machine.
• Timers, that can trigger events after a period of time has passed. The timers:
  • Can be used as count-up or as count-down timers.
  • Can operate in real-time or in virtual-time.

  ARM generic timer的硬件block主要是SOC上的System counter（多个process共享，用来记录时间的流逝）以及附着在各个processor上的Timer（用于触发timer event）组成，其他的generic timer的硬件电路主要是用来进行交流generic time event的。例如各个processor中的timer和system counter外设进行交互，各个processor中的timer进行信息交互。System counter的功能很简单，就是计算输入时钟已经过了多少个clock，开始的时候是0，每一个clock，System counter会加一。System counter的counter value需要分发到各个timer中，也就是说，从各个timer的角度看，system counter value应该是一致的。Timer其实就是定时器，它可以定义一段指定的时间，当时间到了，就会assert一个外部的输出信号（可以输出到GIC，作为一个interrupt source）。

  从power domain来看，ARM generic timer分成两个部分：System counter和各个Multiprocessor系统中的Timer_x、接口电路等。之所以这么分原因很明显：功耗方面（电源管理）的考量。在power saving mode下，可以shutdown各个processor系统的供电，但是可以保持system counter的供电，这样，至少系统时间可以保持住。

  和power domain类似，clock domain也是不同的，system counter和processor工作在不同的clock下，软件修改了CPU的频率也不会影响system counter的工作节奏，从而也不会改变timer的行为。

1.2.The system counter

  The system counter must be implemented in an always-on power domain.The Generic Timer provides a system counter with the following specification:

• Width
  • At least 56 bits wide.
    The value returned by any 64-bit read of the counter is zero-extended to 64 bits.
• Frequency
  • Increments at a fixed frequency, typically in the range 1-50MHz.
  • Can support one or more alternative operating modes in which it increments by larger amounts at a lower frequency, typically for power-saving.
• Start-up Starts operating from zero.

  To support lower-power operating modes, the counter can increment by larger amounts at a lower frequency. For example, a 10MHz system counter might either increment either:

• By 1 at 10MHz.
• By 500 at 20KHz, when the system lowers the clock frequency, to reduce power consumption.

1.3. PE implementations of the Generic Timer

  Each PE implementation of the Generic Timer provides the following components:

• A physical counter, that gives access to the count value of the system counter.
• A virtual counter, that gives access to virtual time.
• A number of timers. In an implementation where all Exception levels are implemented and can use AArch64 state, the timers that are accessible from AArch64 state are:
  • An EL1 physical timer.
  • A Non-secure EL2 physical timer.
  • An EL3 physical timer.
  • An EL1 virtual timer.
  • A Non-secure EL2 virtual timer.
  • A Secure EL2 virtual timer.
  • A Secure EL2 physical timer.

1.3.1.The output of each implemented timer

• Provides an output signal to the system.
• If the PE interfaces to a Generic Interrupt Controller (GIC), signals a Private Peripheral Interrupt (PPI) to that GIC. In a multiprocessor implementation, each PE must use the same interrupt number for each timer.

1.3.2.Each timer registers

• Is based around a 64-bit CompareValue that provides a 64-bit unsigned upcounter.
• Provides an alternative view of the CompareValue, called the TimerValue, that appears to operate as a 32-bit downcounter.
• Has, in addition, a 32-bit Control register.

  如上所示，每个等级的寄存器都不一样，控制physical timer。其中 CompareValue register, and the TimerValue register用于timer interrupt，这个两个寄存器设置一个即可。

u-boot/arch/arm/mach-socfpga/timer_s10.c：
 14 int timer_init(void)
 15 {
 16     int enable = 0x3;   /* timer enable + output signal masked */
 17     int loadval = ~0;
 18 
 19     /* enable system counter */
 20     writel(enable, SOCFPGA_GTIMER_SEC_ADDRESS);
 21     /* enable processor pysical counter */                                                               
 22     asm volatile("msr cntp_ctl_el0, %0" : : "r" (enable));
 23     asm volatile("msr cntp_tval_el0, %0" : : "r" (loadval));
 24 
 25     return 0;
 26 }

  Generally, a Rich operating system (OS) uses the EL1 Non-secure Physical Timer, and a Trusted OS uses the Secure Physical Timer. For example:

• If EL3, NS-EL1, and S-EL1 use AArch64, there are separate Physical Timer registers for Secure and Non-secure worlds.

  • A Rich OS uses the CNTP_CVAL_EL0 register, the CNTP_TVAL_EL0 , and the CNTP_CTL_EL0 registers.
  • A Trusted OS uses the CNTPS_CVAL_EL1 register, the CNTPS_TVAL_EL1 register, and the CNTPS_CTL_EL1 register.

• If EL3 uses AArch32, the Secure and Non-secure Physical Timer registers are banked.

  • A Rich OS uses the Non-secure banked instances of the CNTP_CTL register, the CNTP_CVAL register, and the CNTP_TVAL register.
  • A Trusted OS uses the Secure instances of the same registers.

1.4.Memory-Mapped System Register Descriptions

1.4.1. Registers

• CNTCR(Counter Control Register)

  • An enable bit for the system counter.
  • An enable bit for Halt-on-Debug. When this is enabled, if the debug halt signal into the system counter is asserted, it halts the system counter. Otherwise, the system counter ignores the state of this halt signal. For more information about Halt-on-Debug, contact ARM.
  • A field that can be written to request a change to the update frequency of the system counter, with a corresponding change to the increment made at each update.

• CNTCV(Counter Count Value register)

  • Indicates the current count value.
  • CNTCV is a 64-bit register.

1.4.2.The memory-mapped view of the counter and timer

  To provide the Generic Timer functionality to any programmable system components that cannot implement a coprocessor interface to the Generic Timer, the Generic Timer specification defines a memory-mapped component that can be placed close to such a component. ARM recommends that the system implementation includes an instance of this memory-mapped structure for each system component requiring memory-mapped access to the Generic Timer.

  The memory map consists of up to 8 timer frames. Each timer frame:

• Provides its own set of timers and associated interrupts.
• Is in its own memory protection region that is:
  • In its own memory protection region, with a system-defined size of 4KB or 64KB.
  • At a start address that is aligned to 4KB.

CNTBaseN/CNTPL0BaseN/CNTCTLBase：

• The base address of a frame is CNTBaseN, where N numbers from 0 up to a maximum permitted value of 7.
• The system provides a second view of each implemented CNTBaseN frame. The base address of the second view of the CNTBaseN frame is CNTPL0BaseN.
• In addition, the system provides a control frame at base address CNTCTLBase.

1.5.Initializing and reading the system counter frequency

  Typically, the system counter frequency is set, using the system control register interface, only during the system boot process. It is set by writing the system counter frequency to the CNTFRQ register. Only software executing in a Secure EL1 mode can write to CNTFRQ.

Note:
  Registers refer to Chapter I1 Memory-Mapped System Register Descriptions in ARMv8-A_Architecture_Reference_Manual_(Issue_A.a).pdf