SD_CLK部分

module sd_clk (
   input  wire         hclk,
   input  wire         hrst_n,
   input  wire  [7:0]  in_clk_divider,
   input  wire         in_sd_clk_enable,
   input  wire         hw_stop_clk,

   output wire         out_sd_clk_dft,
   output wire         fifo_sd_clk,

   input  wire         in_TestMode
);
   reg                 out_sd_clk;
   reg          [7:0]  div_counter;
   wire                divider_0_val;
   wire                out_sd_clk_tp;
   wire                clk_ena_stop;

//----------------------------------------------------------------
// Beginning of main code
//----------------------------------------------------------------
//Overview of the SDCLK generator operation
//The following key signals are used in the rx fifo:-
//hclk is the clk of AHB
//in_clk_divider is the divider if hclk
//in_sd_clk_enable is the output enable SDCLK
//out_sd_clk is the SDCLK for sd card

//----------------------------------------------------------------
//Divide HCLK frequency
//----------------------------------------------------------------

assign divider_0_val = (in_clk_divider == 8'h0);
assign clk_ena_stop = (!in_sd_clk_enable || hw_stop_clk);

always @ (posedge hclk or negedge hrst_n)
begin
   if (hrst_n == 0)
      out_sd_clk <= 1'b0;
   else if (clk_ena_stop || divider_0_val)
      out_sd_clk <= 1'b0;
   else if (div_counter == in_clk_divider - 1)
      out_sd_clk <= ~out_sd_clk;
end

always @ (posedge hclk or negedge hrst_n)
begin
   if (hrst_n == 0)
      div_counter <= 8'b0;
   else if (clk_ena_stop || divider_0_val)
      div_counter <= 8'b0;
   else 
      begin
         if (div_counter == in_clk_divider - 1)
            div_counter <= 8'h0;
         else
            div_counter <= div_counter + 1;
      end
end

//MUX2D2BWP7T U_mux_sd_clk (.Z(fifo_sd_clk), .I0(out_sd_clk), .I1(hclk), .S(divider_0_val));
//MUX2D2BWP7T U_sd_clk_tp (.Z(out_sd_clk_tp), .I0(fifo_sd_clk), .I1(1'b0), .S(clk_ena_stop));
//MUX2D2BWP7T U_sd_clk_out (.Z(out_sd_clk_dft), .I0(out_sd_clk_tp), .I1(hclk), .S(in_TestMode));

MX2X2 U_mux_sd_clk (.Y(fifo_sd_clk), .A(out_sd_clk), .B(hclk), .S0(divider_0_val));
//MX2X2 U_sd_clk_tp (.Y(out_sd_clk_tp), .A(fifo_sd_clk), .B(1'b0), .S0(clk_ena_stop));
TLATNTSCAX4 U_cg_sd_clk (.ECK(out_sd_clk_dft), .SE(1'b0), .E(!clk_ena_stop), .CK(fifo_sd_clk));
MX2X2 U_sd_clk_out (.Y(out_sd_clk_dft), .A(out_sd_clk_tp), .B(hclk), .S0(in_TestMode));

//assign out_sd_clk_dft = (!in_sd_clk_enable || hw_stop_clk) ? 1'b0 : 
//                        (in_TestMode) ? hclk : (in_clk_divider == 8'h0) ? hclk : out_sd_clk;

endmodule