c语言加法器程序代码,利用EDA设计加法器和减法器并且附有程序代码的实验报告...

满意答案

q316281484

2013.12.31

采纳率：48%    等级：12

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library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity full is

port(cin:in std_logic;

a,b:in std_logic_vecter(7downto 0);

s :out std_logic_vecter(7downto 0);

cout:out std_logic

);

end full;

architecture beh of full is

signal sint:std_logic_vector(8 downto 0);

signal aa,bb:std_logic_vector(8 downto 0);

begin

aa<='0'&a(7downto 0);

bb<='0'&b(7downto 0);

sint<=aa+bb+cin;

s(7 downto 0)<=sint(7 downto 0):

cout<=sint(4);

end a;

这个是8位加法器

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity jfq is

port(sub:in std_logic;

a,b:in std_logic_vector(3 downto 0);

s :out std_logic_vector(3 downto 0);

cout:out std_logic

);

end jfq;

architecture beh of jfq is

signal a1,a2,a3:std_logic(3 downto 0);

begin

a1<='0'&a(3 downto 0);

a2<='0'&b(3 downto 0);

a3<=a1-a2-sub;

s<=a3(3 downto 0);

cout<=a3(3 downto 0);

end beh;

这个是4未减法器

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