前言:
一,verilog加法器设计
1,半加器
(1)代码
module h_adder(A,B,SO,CO);
input A,B;
output SO,CO;
assign SO= A^B;
assign CO= A&B;
endmodule
2,全加器
(1)代码
module f_adder(ain,bin,cin,cout,sum);
output cout,sum;
input ain,bin,cin;
wire net1,net2,net3;
h_adder U1(ain,bin,net1,net2);
h_adder U2(.A(net1),.SO(sum),.B(cin),.CO(net3));
or U3(cout,net2,net3);
endmodule
(2)仿真结果
3,算数运算符
module test1(A,B,C,D,RCD,RAB,RM1,RM2,S,C0,R1,R2);
input [3:0] C,D; input [3:0] A,B;
output [3:0] RCD; output [3:0]RAB;
output [7:0] RM1; output [7:0] RM2;
output [3:0] S; output C0;
output R1,R2;
reg[3:0] S; reg C0;
reg[3:0] RCD; reg[7:0] RM1;
reg signed[3:0]RAB; reg signed[7:0]RM2;
reg R1,R2;
always@ (A,B,C,D)begin
RCD <= C+D;
RAB <= A+B;
RM1 <= C*D;
RM2 <= A*B;
{C0,S} <= {1'b0,C} - {1'b0,D};
R1<= (C>D);
R2<= (A>B);
end
endmodule
(1)仿真代码
(2)显示16进制
(3)仿真显示
5,BCD码加法器
(1)代码
module BCD_ADDER(A,B,D);
input [7:0]A,B; output[8:0]D;
wire [4:0] DT0,DT1; reg[8:0]D; reg S;
always@(DT0)
begin
if (DT0[4:0]>=5'b01010)
begin D[3:0]=(DT0[3:0]+4'b0110); S=1'b1;end
else begin D[3:0]=DT0[3:0]; S=1'b0;end
end
always@(DT1)
begin
if (DT1[4:0]>=5'b01010)
begin D[7:4] = (DT1[3:0]+4'b0110); D[8]=1'b1; end
else begin D[7:4] =DT1[3:0]; D[8]=1'b0; end
end
assign DT0=A[3:0]+B[3:0];
assign DT1=A[7:4]+B[7:4]+S;
endmodule