数字IC必修之Verilog知识点——模块建立及常用语法总结过程块中的语法(面试小白考试)

  1. Module

    module my_module(out1,…,inN) ;
    output out1,…,outM;
    input in1,…,inN;
    …// declarations
    …// description of f (maybe sequential)
    endmodule

  2. Continuous Assignments
    assign #de1 (net type) = expr;

    inside a module
    outside procedures(always可综合 initial不可综合)
    they all execute in parallel
    are order independent
    are continuously active

  3. Structural Model(Gate level)

    and,nand,nor,or,xor,xnor,buf,not,bufifo,bufif1,notif0,notif1

  4. Behavioral Model-Procedures

    进程并行执行

  5. Block statement

    Sequential(begin-end blocks)
    Parallel (fork-join blocks) 不可综合的

    begin
    a = 1;
    #10 a = 0;
    #5 a = 4; //按顺序执行 #15时候 a=4
    end

    fork
    a=1;
    #10 a=0;
    #5 a =4; //3条语句同时执行所以#5时a=4 #10 a =0
    join

  6. 时间不可综合

    wait 不可综合,用于仿真

  7. always @(level, posedge clk)
    always @(level, negedge clk)
    level 电平触发
    sensitive list 时候组合电路必须要把所有输入放进去

  8. 电平触发的DFF 是个锁存器

  9. Procedural Statements: if 有优先级

    if (expr1)
    xxxx;
    else if()
    xxxx;
    else
    xxxx;

    没有else匹配会生成锁存器(这种锁存器对电路也有好处(忘记了是啥好处了))

  10. Procedural Statements: case

    case(expr)
    x’b xx : xxxx;
    .
    .
    .
    defoult : xxx;
    endcase

  11. Procedural Statements: for
    for(init_assignment; cond;step_assignment)

    for(i = 0; i<3 ; i = i+1)
    xxxx;

    for循环能不能综合取决于循环次数是否是确定的,如果循环次数是确定的则可以综合

  12. Procedural Statements: while 不可综合
    while (expr) stmt;

    while (i<3) begin
    Y = Y+1;
    i = i+1; //循环增量在循环中产生
    end

  13. Procedural Statements: repeat 不可综合
    repeat(times) stmt;

  14. Procedural Statements: forever 不可综合
    forever stmt; 一直执行到仿真结束
    clock generation

    创建时钟
    reg clk;
    initial begin
    clk = 0;
    forever # 10 clk = ~clk;
    end

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