5 Building Larger Circuits
5.1 Counter with period 1000(Exams/review2015 count1k)
module top_module (
input clk ,
input reset ,
output [ 9 : 0 ] q ) ;
always @ ( posedge clk ) begin
if ( reset ) begin
q <= 10 'd0 ;
end
else if ( q == 10 'd999 ) begin
q <= 10 'd0 ;
end
else begin
q <= q + 1 'd1 ;
end
end
endmodule
5.2 4-bit shift register and down counter(Exams/review2015 shiftcount)
module top_module (
input clk ,
input shift_ena ,
input count_ena ,
input data ,
output [ 3 : 0 ] q ) ;
always @ ( posedge clk ) begin
if ( shift_ena ) begin
q <= { q [ 2 : 0 ] , data } ;
end
else if ( count_ena ) begin
q <= q - 1 'd1 ;
end
end
endmodule
5.3 FSM:Sequence 1101 recognizer(Exams/review2015 fsmseq)
module top_module (
input clk ,
input reset , // Synchronous reset
input data ,
output start_shifting ) ;
// 状态机三段法
// 参数声明
parameter IDLE = 3 'd0 , S1 = 3 'd1 , S2 = 3 'd2 , S3 = 3 'd3 , S4 = 3 'd4 ;
// 内部信号声明
reg [ 2 : 0 ] state , next_state ;
// 状态寄存器(时序)
always @ ( posedge clk ) begin
if ( reset ) begin
state <= IDLE ;
end
else begin
state <= next_state ;
end
end
// 次态的组合逻辑
always @ ( * ) begin
case ( state )
IDLE : begin
if ( data == 1 'b1 ) begin
next_state = S1 ;
end
else begin
next_state = IDLE ;
end
end
S1 : begin
if ( data == 1 'b1 ) begin
next_state = S2 ;
end
else begin
next_state = IDLE ;
end
end
S2 : begin
if ( data == 1 'b1 ) begin
next_state = S2 ;
end
else begin
next_state = S3 ;
end
end
S3 : begin
if ( data == 1 'b1 ) begin
next_state = S4 ;
end
else begin
next_state = IDLE ;
end
end
S4 : begin
next_state = S4 ;
end
endcase
end
// 输出逻辑
always @ ( * ) begin
if ( state == S4 ) begin
start_shifting = 1 'b1 ;
end
else begin
start_shifting = 1 'b0 ;
end
end
endmodule
5.4 FSM: Enable shift register(Exams/review2015 fsmshift)
module top_module (
input clk ,
input reset , // Synchronous reset
output shift_ena ) ;
// 状态机三段法
// 参数声明
parameter IDLE = 3 'd0 , S1 = 3 'd1 , S2 = 3 'd2 , S3 = 3 'd3 , S4 = 3 'd4 ;
// 内部信号声明
reg [ 2 : 0 ] state , next_state ;
// 状态寄存器(时序)
always @ ( posedge clk ) begin
if ( reset ) begin
state <= IDLE ;
end
else begin
state <= next_state ;
end
end
// 次态的组合逻辑
always @ ( * ) begin
case ( state )
IDLE : begin
next_state = S1 ;
end
S1 : begin
next_state = S2 ;
end
S2 : begin
next_state = S3 ;
end
S3 : begin
next_state = S4 ;
end
S4 : begin
next_state = S4 ;
end
default : begin
next_state = S4 ;
end
endcase
end
// 输出逻辑
always @ ( * ) begin
if ( state == S4 ) begin
shift_ena = 1 'b0 ;
end
else begin
shift_ena = 1 'b1 ;
end
end
endmodule
5.5 FSM: The complete FSM(Exams/review2015 fsm)
module top_module (
input clk ,
input reset , // Synchronous reset
input data ,
output shift_ena ,
output counting ,
input done_counting ,
output done ,
input ack ) ;
// 状态及三段式
// 参数定义
parameter IDLE = 4 'd0 , S1 = 4 'd1 , S11 = 4 'd2 , S110 = 4 'd3 , B0 = 4 'd4 , B1 = 4 'd5 , B2 = 4 'd6 , B3 = 4 'd7 , COUNT = 4 'd8 , WAIT = 4 'd9 ;
reg [ 3 : 0 ] state , next_state ;
// 状态寄存器(时序)
always @ ( posedge clk ) begin
if ( reset ) begin
state <= IDLE ;
end
else begin
state <= next_state ;
end
end
// 次态的组合逻辑
always @ ( * ) begin
case ( state )
IDLE : begin
next_state = data ? S1 : IDLE ;
end
S1 : begin
next_state = data ? S11 : IDLE ;
end
S11 : begin
next_state = data ? S11 : S110 ;
end
S110 : begin
next_state = data ? B0 : IDLE ;
end
B0 : begin
next_state = B1 ;
end
B1 : begin
next_state = B2 ;
end
B2 : begin
next_state = B3 ;
end
B3 : begin
next_state = COUNT ;
end
COUNT : begin
next_state = done_counting ? WAIT : COUNT ;
end
WAIT : begin
next_state = ack ? IDLE : WAIT ;
end
default : begin
next_state = IDLE ;
end
endcase
end
// 输出逻辑
always @ ( * ) begin
if ( state == B0 || state == B1 || state == B2 || state == B3 ) begin
shift_ena = 1 'b1 ;
end
else begin
shift_ena = 1 'b0 ;
end
end
always @ ( * ) begin
if ( state == COUNT ) begin
counting = 1 'b1 ;
end
else begin
counting = 1 'b0 ;
end
end
always @ ( * ) begin
if ( state == WAIT ) begin
done = 1 'b1 ;
end
else begin
done = 1 'b0 ;
end
end
endmodule
5.6 The complete timer(Exams/review2015 fancytimer)
module top_module (
input clk ,
input reset , // Synchronous reset
input data ,
output [ 3 : 0 ] count ,
output counting ,
output done ,
input ack ) ;
// 状态机三段式
// 参数定义
parameter S = 0 , S1 = 1 , S11 = 2 , S110 = 3 , B0 = 4 , B1 = 5 , B2 = 6 , B3 = 7 , COUNT_REG = 8 , WAIT = 9 ;
reg [ 3 : 0 ] state ;
reg [ 3 : 0 ] next_state ;
reg [ 3 : 0 ] par_in ;
状态寄存器(时序)
reg [ 15 : 0 ] counter ;
always @ ( posedge clk ) begin
if ( reset ) begin
counter <= 16 'd0 ;
end
else if ( next_state == WAIT ) begin
counter <= 16 'd0 ;
end
else if ( next_state == COUNT_REG ) begin
counter <= counter + 1 'b1 ;
end
end
reg [ 3 : 0 ] a ;
always @ ( * ) begin
if ( counter <= 1000 ) begin
a = 4 'd0 ;
end
if ( counter > 1000 && counter <= 2000 ) begin
a = 4 'd1 ;
end
if ( counter > 2000 && counter <= 3000 ) begin
a = 4 'd2 ;
end
if ( counter > 3000 && counter <= 4000 ) begin
a = 4 'd3 ;
end
if ( counter > 4000 && counter <= 5000 ) begin
a = 4 'd4 ;
end
if ( counter > 5000 && counter <= 6000 ) begin
a = 4 'd5 ;
end
if ( counter > 6000 && counter <= 7000 ) begin
a = 4 'd6 ;
end
if ( counter > 7000 && counter <= 8000 ) begin
a = 4 'd7 ;
end
if ( counter > 8000 && counter <= 9000 ) begin
a = 4 'd8 ;
end
if ( counter > 9000 && counter <= 10000 ) begin
a = 4 'd9 ;
end
if ( counter > 10000 && counter <= 11000 ) begin
a = 4 'd10 ;
end
if ( counter > 11000 && counter <= 12000 ) begin
a = 4 'd11 ;
end
if ( counter > 12000 && counter <= 13000 ) begin
a = 4 'd12 ;
end
if ( counter > 13000 && counter <= 14000 ) begin
a = 4 'd13 ;
end
if ( counter > 14000 && counter <= 15000 ) begin
a = 4 'd14 ;
end
if ( counter > 15000 && counter <= 16000 ) begin
a = 4 'd15 ;
end
end
wire b ;
assign b = ( counter == ( par_in + 1 ) * 1000 ) ? 1 'b1 : 1 'b0 ;
// 次态的组合逻辑
always @ ( posedge clk ) begin
if ( reset ) begin
state <= S ;
end
else begin
state <= next_state ;
end
end
always @ ( * ) begin
case ( state )
S : begin
next_state = data ? S1 : S ;
end
S1 : begin
next_state = data ? S11 : S ;
end
S11 : begin
next_state = data ? S11 : S110 ;
end
S110 : begin
next_state = data ? B0 : S ;
end
B0 : begin
next_state = B1 ;
par_in [ 3 ] = data ;
end
B1 : begin
next_state = B2 ;
par_in [ 2 ] = data ;
end
B2 : begin
next_state = B3 ;
par_in [ 1 ] = data ;
end
B3 : begin
next_state = COUNT_REG ;
par_in [ 0 ] = data ;
end
COUNT_REG : begin
next_state = b ? WAIT : COUNT_REG ;
end
WAIT : begin
next_state = ack ? S : WAIT ;
end
default : begin
next_state = S ;
end
endcase
end
// 输出逻辑
assign count = ( state == COUNT_REG ) ? ( par_in - a ) : 4 'd0 ;
assign counting = ( state == COUNT_REG ) ;
assign done = ( state == WAIT ) ;
endmodule
5.7 FSM: One-hot logic equations(Exams/review2015 fsmonehot)
module top_module (
input d ,
input done_counting ,
input ack ,
input [ 9 : 0 ] state , // 10 - bit one - hot current state
output B3_next ,
output S_next ,
output S1_next ,
output Count_next ,
output Wait_next ,
output done ,
output counting ,
output shift_ena
) ; //
// You may use these parameters to access state bits using e . g . , state [ B2 ] instead of state [ 6 ] .
parameter S = 0 , S1 = 1 , S11 = 2 , S110 = 3 , B0 = 4 , B1 = 5 , B2 = 6 , B3 = 7 , Count = 8 , Wait = 9 ;
// 根据状态转换图分析输出即可
assign B3_next = state [ B2 ] ;
assign S_next = ~ d & state [ S ] | ~ d & state [ S1 ] | ~ d & state [ S110 ] | ack & state [ Wait ] ;
assign S1_next = d & state [ S ] ;
assign Count_next = state [ B3 ] | ~ done_counting & state [ Count ] ;
assign Wait_next = done_counting & state [ Count ] | ~ ack & state [ Wait ] ;
assign done = state [ Wait ] ;
assign counting = state [ Count ] ;
assign shift_ena = state [ B0 ] | state [ B1 ] | state [ B2 ] | state [ B3 ] ;
endmodule