FPGA实现二进制转BCD码

Verilog代码：
module Binary_to_BCD
#(parameter INPUT_WIDTH,
parameter DECIMAL_DIGITS)
(
input i_Clock,
input [INPUT_WIDTH-1:0] i_Binary,
input i_Start,
//
output [DECIMAL_DIGITS*4-1:0] o_BCD,
output o_DV
);

parameter s_IDLE = 3’b000;
parameter s_SHIFT = 3’b001;
parameter s_CHECK_SHIFT_INDEX = 3’b010;
parameter s_ADD = 3’b011;
parameter s_CHECK_DIGIT_INDEX = 3’b100;
parameter s_BCD_DONE = 3’b101;

reg [2:0] r_SM_Main = s_IDLE;

// The vector that contains the output BCD
reg [DECIMAL_DIGITS*4-1:0] r_BCD = 0;

// The vector that contains the input binary value being shifted.
reg [INPUT_WIDTH-1:0] r_Binary = 0;

// Keeps track of which Decimal Digit we are indexing
reg [DECIMAL_DIGITS-1:0] r_Digit_Index = 0;

// Keeps track of which loop iteration we are on.
// Number of loops peRFormed = INPUT_WIDTH
reg [7:0] r_Loop_Count = 0;

wire [3:0] w_BCD_Digit;
reg r_DV = 1’b0;

always @(posedge i_Clock)
begin

  case (r_SM_Main) 

    // Stay in this state until i_Start comes along
    s_IDLE :
      begin
        r_DV <= 1'b0;
         
        if (i_Start == 1'b1)
          begin
            r_Binary  <= i_Binary;
            r_SM_Main <= s_SHIFT;
            r_BCD     <= 0;
          end
        else
          r_SM_Main <= s_IDLE;
      end