Overview of Register Model

A register model is typically composed of a hierarchy of blocks that map to the design hierarchy. Blocks can contain registers, register files and memories, as well as other blocks. The register layer classes support front-door and back-door access to provide redundant paths to the register and memory implementation, and verify the correctness of the decoding and access paths, as well as increased performance after the physical access paths have been verified. Designs with multiple physical interfaces, as well as registers, register files, and memories shared across multiple interfaces, are also supported.

An example: F1 shows the structure of a sample design block containing two registers, which have two and three fields respectively, an internal memory, and an external memory.

F2 shows the structure of the corresponding register model.

When using a register model, fields, registers, and memory locations are accessed through read and write methods in their corresponding abstraction class. It is the responsibility of the register model to turn these abstracted accesses into read and write cycles at the appropriate addresses via the appropriate bus driver. A register model user never needs to track the specific address or location of a field, register, or memory location, only its name.

• Reading the field ADDR in the CONFIG register: CODEC.CONFIG.ADDR.read()
• location 7 in the BFR memory can be accessed using CODEC.BFR.write(7,value)