我也要用
verilog
绝不做九漏鱼
这个作者很懒，什么都没留下…
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原创 【verilog】设计一个测试文件，产生一个周期为2微秒，占空比为3:1的时钟信号
〇、前情提要 帮可爱的涛涛看题，顺便复习一下verilog。 参考： Verilog测试：TestBench结构 https://blog.csdn.net/qq_26652069/article/details/96422293 占空比的故事 http://www.360doc.com/content/18/0928/00/11935121_790268293.shtml Verilog仿真时钟产生方法学习 https://blog.csdn.net/flomingo1/article/details2020-11-30 10:44:32
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原创 【verilog】b站-[Verilog HDL] Installing and Testing Icarus Verilog + GTKWave 笔记
〇、前情提要 In this lesson we’ll go through the installation (Windows) for Icarus and GTKWave and write a very simple, hello world, style module and testbench. 参考： b站视频 - [Verilog HDL] Installing and Testing Icarus Verilog + GTKWave https://www.bilibili.com/vi2020-11-30 10:20:13
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