FPGA学习笔记1--1位全加器

module full_adder1(
input a,
input b,
input cin,
output sum,
output cout);
assign sum=a^b^cin;
assign cout=(a&b)|(b&cin)|(a&cin);

endmodule

仿真代码

`timescale 1ns/1ns 
`include "full_adder1.v" 
module tb_full_adder1();
reg a;
reg b;
reg cin;
wire sum;
wire cout;
full_adder1 u1(.a(a),.b(b),.cin(cin),
.sum(sum),.cout(cout));
initial begin
a=1'b0;
b=1'b0;
cin=1'b0;
end
always #5 a=~a;
always #10 b=~b;
always # 15 cin=~cin;
endmodule

波形：