FPGA学习笔记22--可调加法/减法计数器

module updowncount(
input [7:0]d,
input clk, rst_n,load,
input up_down,
output reg [7:0]cnt
);

always@(posedge clk or negedge rst_n )begin
	if(!rst_n) cnt=8'h00;
	else if(load) cnt=d;
	else if(up_down) cnt=cnt+1;
	else cnt=cnt-1;
end
endmodule

`timescale 1ns/1ns
module tb_up_down_count();
reg [7:0]d;
reg clk, rst_n,load;
reg up_down;
wire [7:0]cnt;

updowncount u1(.clk(clk),.d(d),.rst_n(rst_n),.load(load),.up_down(up_down),.cnt(cnt));
initial begin
d<=8'd52;
clk<=1'b0;
rst_n<=1'b0;
load<=1'b0;
up_down<=1'b1;
#50 rst_n<=~rst_n;

end
always #5 clk<=~clk;
always #200 up_down<=~up_down;
always #500 load<=~load;


endmodule