module rom(addr,data);
input[3:0] addr;
output[7:0] data;
function[7:0] romout;
input[3:0] addr;
case(addr)
0 : romout = 0;
1 : romout = 1;
2 : romout = 4;
3 : romout = 9;
4 : romout = 16;
5 : romout = 25;
6 : romout = 36;
7 : romout = 49;
8 : romout = 64;
9 : romout = 81;
10 : romout = 100;
11 : romout = 121;
12 : romout = 144;
13 : romout = 169;
14 : romout = 196;
15 : romout = 225;
default : romout = 8'hxx;
endcase
endfunction
assign data = romout(addr);
endmodule
`timescale 1ns/1ns
module tb_rom();
reg [3:0] addr;
wire[7:0] data;
rom u1(.addr(addr),.data(data));
initial begin
addr=4'd10;
#50 addr=4'd12;
end
endmodule
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