Circuits--Sequential Logic--Finite State Machines--Lemmings2

网址：https://hdlbits.01xz.net/wiki/Lemmings2

module top_module(
    input clk,
    input areset,    // Freshly brainwashed Lemmings walk left.
    input bump_left,
    input bump_right,
    input ground,
    output walk_left,
    output walk_right,
    output aaah ); 
    
    parameter [2:0]  LEFT = 3'b001;
    parameter [2:0]  RIGHT = 3'b010;
    parameter [2:0] AAAH = 3'b100;
  
    
    reg  [2:0] state;
    reg  [2:0] next_state;
    reg  [2:0] last_state;

    
    always@(posedge clk or posedge areset)
        begin
            if(areset)
                state <=LEFT;
            else
                state <= next_state;
        end
    
    always@(*)
        case(state)
            LEFT:
                begin
                    if(bump_left == 1'b1)
                        begin
                            if(ground == 1'b0)
                        		begin
                        		next_state <= AAAH;
                        		last_state <= LEFT;
                        		end
                            else
                            	begin
                            	next_state <= RIGHT;
                            	last_state <= RIGHT;
                       			end     
                        end
                    else if(ground == 1'b0)
                        begin
                        next_state <= AAAH;
                        last_state <= LEFT;
                        end
                    else
                        next_state <= LEFT;
                end
            RIGHT:
                begin
                    if(bump_right == 1'b1)
                        begin
                            if(ground == 1'b0)
                        		begin
                        		next_state <= AAAH;
                        		last_state <= RIGHT;
                        		end
                            else
                            	begin
                            	next_state <= LEFT;
                            	last_state <= LEFT;
                       			end     
                        end
                    else if(ground == 1'b0)
                        begin
                        next_state <= AAAH;
                        last_state <= RIGHT;
                        end
                    else
                        next_state <= RIGHT;
                end
            AAAH:
                begin
                    if(ground == 1'b0)
                        next_state <= AAAH;
                    else 
                        next_state <= last_state;
                end
   default:
                    next_state <= LEFT;
        endcase
    
    assign walk_left = (state == LEFT);
    assign walk_right = (state == RIGHT);
    assign aaah = (state == AAAH);
        

endmodule