Circuits--Sequential Logic--Finite State Machines--Lemmings4

网址：https://hdlbits.01xz.net/wiki/Lemmings4

module top_module(
    input clk,
    input areset,    // Freshly brainwashed Lemmings walk left.
    input bump_left,
    input bump_right,
    input ground,
    input dig,
    output walk_left,
    output walk_right,
    output aaah,
    output digging); 
    
    parameter	[4:0]  LEFT = 	5'b00001;
    parameter	[4:0]	RIGHT = 5'b00010;
    parameter	[4:0]	AAAH = 	5'b00100;
    parameter	[4:0]	DIG	= 	5'b01000;
    parameter	[4:0]	SPLA =  5'b10000;
    
    reg		[4:0]	cnt;
    reg				flag;
    parameter	[4:0]	spla_MAX = 5'd19;
    
    reg	 	[4:0]	state	;
    reg		[4:0]	next_state;
    reg		[4:0]	last_state;
    
    always@(posedge clk or posedge areset)
      begin
          if(areset)
              cnt <= 5'd0;
          else if(next_state == AAAH)
              cnt <= cnt + 5'd1;
          else
              cnt <= 5'd0;
      end  
    
    always@(posedge clk or posedge areset)
      begin
          if(areset)
              flag <= 1'b0;
          else if(cnt > spla_MAX)
              flag <= 1'b1;
          else
              flag <= flag;
      end 
    
    always@(posedge clk or posedge areset)
        begin
            if(areset)
                state <= LEFT;
            else
                state <= next_state;
        end
    
    always@(*)    begin
        case(state)
            LEFT:
                begin
                    if(ground == 1'b0)
                        begin
                            next_state <= AAAH;
                            last_state <= LEFT;
                        end
                    else 	if(dig == 1'b1)
                        begin  
                            next_state <= DIG;
                            last_state <= LEFT;
                        end
                    else	if(bump_left == 1'b1)
                        begin
                            next_state <= RIGHT;
                            last_state <= RIGHT;
                        end
                    else
                        begin
                        next_state <= LEFT;
                        last_state <= LEFT;
                        end
                end
            RIGHT:
                begin
                    if(ground == 1'b0)
                        begin
                            next_state <= AAAH;
                            last_state <= RIGHT;
                        end
                    else 	if(dig == 1'b1)
                        begin  
                            next_state <= DIG;
                            last_state <= RIGHT;
                        end
                    else	if(bump_right == 1'b1)
                        begin
                            next_state <= LEFT;
                            last_state <= LEFT;
                        end
                    else
                        begin
                        next_state <= RIGHT;
                        last_state <= RIGHT;
                        end
                end
            AAAH:
                begin
                    if(ground == 1'b0)
                        next_state <= AAAH;
                    else if(flag == 1'b1)
                        next_state <= SPLA;
                    else 
                        next_state <= last_state;
                end
             DIG:
                begin
                    if(ground == 1'b1)
                        next_state <= DIG;
                    else
                        next_state <= AAAH;
                end
            SPLA:
                		next_state <= SPLA;

   default:
       			begin
                    next_state <= LEFT;
                    last_state <= LEFT;
                end
        endcase
        end
    
    assign walk_left = (state == LEFT);
    assign walk_right = (state == RIGHT);
    assign aaah = (state == AAAH);
    assign digging =(state == DIG); 
                
                     

endmodule