hdlbit Lemmings4练习

Lemmings4练习原题如下：

注意：若想仿真正确，计数值counter位宽要设大一些，原先我设置了5bit，结果仿真不正确，更改为8bit后结果正确，因为位宽小的话计数结果可能会溢出（或者counter增大一定数组时候之后就不增加了，本文采用后一种方法）
状态转移图如下：

代码如下：

module top_module(
    input clk,
    input areset,    // Freshly brainwashed Lemmings walk left.
    input bump_left,
    input bump_right,
    input ground,
    input dig,
    output walk_left,
    output walk_right,
    output aaah,
    output digging ); 

    parameter FALL_L = 3'b000,FALL_R = 3'b001,LEFT=3'b010, RIGHT=3'b011;
    parameter dig_L  = 3'b100, dig_R = 3'b101,Die = 3'b111;
    reg [2:0] state, next_state;
    reg [7:0] counter;
    //计数器
    always @(posedge clk, posedge areset)
        begin
            if(areset)
            counter = 5'd0;      
            else if(state == FALL_R || state == FALL_L && (counter < 5'd30)) //防止溢出
            counter = counter + 5'd1; 
            else if(state == FALL_R || state == FALL_L) 
            counter = counter; 
            else
            counter = 5'd0;      
        end
   
  
    always @(*) begin
        // State transition logic
        case(state)
            LEFT:
                begin
                    if(!ground)
                        begin
                            next_state = FALL_L; 
                        end
                    else if(dig)
                        begin
                            next_state = dig_L; 
                        end
                    else if(!bump_left)
                        next_state = LEFT;
                    else
                        next_state = RIGHT;
                end
            RIGHT: 
                begin
                      if(!ground)
                          begin
                              next_state = FALL_R; 
                          end
                    else if(dig)
                        begin
                            next_state = dig_R; 
                        end
                    else if(!bump_right)
                        next_state = RIGHT;
                    else
                        next_state = LEFT;
                end
            FALL_L: 
                begin
                      if(!ground)
                        next_state = FALL_L; 
                    else if(counter >= 5'd20)
                        next_state = Die; 
                      else
                        next_state = LEFT;
                end
             FALL_R: 
                begin
                      if(!ground)
                        next_state = FALL_R; 
                    else if(counter >= 5'd20)
                        next_state = Die; 
                       else
                        next_state = RIGHT;
                end
             dig_L: 
                begin
                      if(!ground)
                        next_state = FALL_L; 
                     else 
                         next_state = dig_L; 
                      
                end
             dig_R: 
                begin
                       if(!ground)
                        next_state = FALL_R;  
                       else
                        next_state = dig_R;
                end
               Die: 
                begin
                      next_state = Die;
                end
        default:  next_state = LEFT;
        endcase
    end

   always @(posedge clk, posedge areset)
    begin
        // State flip-flops with asynchronous reset
        if(areset)
            state <= LEFT;
        else
            state <= next_state;
    end

    // Output logic
    assign walk_left  = (state == Die) ? 1'b0 : (state == LEFT)  ;
    assign walk_right = (state == Die) ? 1'b0 : (state == RIGHT) ;
    assign aaah       = (state == Die) ? 1'b0 : (state == FALL_R || state == FALL_L);
    assign digging    = (state == Die) ? 1'b0 : (state == dig_L  || state == dig_R);
endmodule

仿真结果如下：