HDLBits练习-Build a circuit dorm a smulation waveform

HDLBits练习

Verification:Reading Simulations-Build a circuit dorm a smulation waveform

题1：Combinational circuit 1

module top_module (
    input a,
    input b,
    output q );//

    assign q = a & b; // Fix me

endmodule

题2：Combinational circuit 2

module top_module (
    input a,
    input b,
    input c,
    input d,
    output q );//

    assign q = (~a & ~b & ~c & ~d) | (a & b & ~c & ~d) | (~a & b & ~c & d) | (a & ~b & ~c & d) | (~a & ~b & c & d) | (a & b & c & d) | (~a & b & c & ~d) | (a & ~b & c & ~d); // Fix me

endmodule

题3：Combinational circuit 3

module top_module (
    input a,
    input b,
    input c,
    input d,
    output q );//

    assign q = a & d | (~a & b & d) | (a & c & ~d) | (b & c & ~d); // Fix me

endmodule

题4：Combinational circuit 4

module top_module (
    input a,
    input b,
    input c,
    input d,
    output q );//

    assign q = b | (~a & ~b & c) | (a & ~b & c); // Fix me

endmodule

题5：Combinational circuit 5

module top_module (
    input [3:0] a,
    input [3:0] b,
    input [3:0] c,
    input [3:0] d,
    input [3:0] e,
    output [3:0] q );
    always@(*)begin
        case(c)
            4'd0: q=b;
            4'd1: q=e;
            4'd2: q=a;
            4'd3: q=d;
            default: q=4'hf;
        endcase
    end
endmodule

题6：Combinational circuit 6

module top_module (
    input [2:0] a,
    output [15:0] q ); 
    always@(*)begin
        case(a)
            3'd0:q=16'h1232;
            3'd1:q=16'haee0;
            3'd2:q=16'h27d4;
            3'd3:q=16'h5a0e;
            3'd4:q=16'h2066;
            3'd5:q=16'h64ce;
            3'd6:q=16'hc526;
            3'd7:q=16'h2f19;
        endcase
    end
endmodule

题7：Combinational circuit 7

module top_module (
    input clk,
    input a,
    output q );
    always@(posedge clk)begin
        q<=~a;
    end
endmodule

题8：Combinational circuit 8

module top_module (
    input clock,
    input a,
    output p,
    output q );
    assign p=(clock)? a : p;
    always@(negedge clock)begin
        q=p;
    end
endmodule

题9：Combinational circuit 9

module top_module (
    input clk,
    input a,
    output [3:0] q );
    always @(posedge clk) begin
        q<=(a)? 4'd4 : ((q==4'd6)? 4'd0 : q+1'd1);
    end
endmodule

题10：Combinational circuit 10

module top_module (
    input clk,
    input a,
    input b,
    output q,
    output state  );
	always @(posedge clk) begin
        if(a & b)begin
            state<=1'd1;
        end
        else if(~a & ~b)begin
            state<=1'd0;
        end
        else begin
            state<=state;
        end
    end
    assign q = a ^ b ^ state;
endmodule