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HDLBits练习
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HDLBits练习-Verfication: Writing Testbenches
HDLBits练习Verfication: Writing Testbenches题1:Clockmodule top_module (); reg clk; always begin clk=1'b0; #5 clk=1'b1; #5; end dut u0(.clk(clk));endmodule题2: Testbench1module top_module ( output reg A, outp原创 2021-07-23 15:06:33 · 178 阅读 · 0 评论 -
HDLBits练习-Build a circuit dorm a smulation waveform
HDLBits练习Verification:Reading Simulations-Build a circuit dorm a smulation waveform题1:Combinational circuit 1module top_module ( input a, input b, output q );// assign q = a & b; // Fix meendmodule题2:Combinational circuit 2modu原创 2021-07-23 11:02:30 · 123 阅读 · 0 评论 -
HDLBits练习-Finding bugs in code
HDLBits练习Verification:Reading Simulations-Finding bugs in code题目1:Muxmodule top_module ( input sel, input [7:0] a, input [7:0] b, output [7:0]out ); assign out = (sel)? a : b;endmodule题目2:NAND原创 2021-07-22 19:42:57 · 124 阅读 · 0 评论 -
HDLBits练习-Building Larger Circuits
HDLBits练习Circuits-Building Larger Circuits题1:Counter with period 1000module top_module ( input clk, input reset, output [9:0] q); always@(posedge clk)begin if(reset) q<=10'd0; else q<=(q==10'd99原创 2021-07-22 18:58:01 · 146 阅读 · 0 评论 -
HDLBits练习-有限状态机(FSM)(6)
HDLBits练习Circuits-Sequential Logic-Finite State Machines(6)题32:Q2a: FSMmodule top_module ( input clk, input resetn, // active-low synchronous reset input [3:1] r, // request output [3:1] g // grant); parameter A=2'd0,B=2'd1,C=2'原创 2021-06-28 11:09:49 · 167 阅读 · 0 评论 -
HDLBits练习-有限状态机(FSM)(5)
HDLBits练习Circuits-Sequential Logic-Finite State Machines(5)题25:Q3b: FSMmodule top_module ( input clk, input reset, // Synchronous reset input x, output z); reg [2:0]state,next_state; always@(*)begin case(state)原创 2021-05-21 17:29:37 · 250 阅读 · 0 评论 -
HDLBits练习-有限状态机(FSM)(4)
HDLBits练习Circuits-Sequential Logic-Finite State Machines(4)题20:Sequence recognitionmodule top_module( input clk, input reset, // Synchronous reset input in, output disc, output flag, output err ); reg [3:0]state,next_s原创 2021-05-10 17:29:57 · 187 阅读 · 0 评论 -
HDLBits练习-有限状态机(FSM)(3)
HDLBits练习Circuits-Sequential Logic-Finite State Machines(3)题14:One-hot FSMmodule top_module( input in, input [9:0] state, output [9:0] next_state, output out1, output out2); assign next_state[0]=~in & (|{state[4:0], state[9:7原创 2021-05-06 17:30:08 · 200 阅读 · 0 评论 -
HDLBits练习-有限状态机(FSM)(2)
HDLBits练习Circuits-Sequential Logic-Finite State Machines(2)题9:Design a Moore FSMmodule top_module ( input clk, input reset, input [3:1] s, output fr3, output fr2, output fr1, output dfr); reg [2:0]sd; always@(posedg原创 2021-05-05 23:22:58 · 200 阅读 · 0 评论 -
HDLBits练习-有限状态机(FSM)(1)
HDLBits练习Circuits-Sequential Logic-Finite State Machines(1)题1:Simple FSM 1 (asynchronous reset)module top_module( input clk, input areset, // Asynchronous reset to state B input in, output out); parameter A=0, B=1; reg state原创 2021-04-22 14:26:31 · 276 阅读 · 1 评论 -
HDLBits练习——More Circuits
HDLBits练习Circuits-Sequential Logic-More Circuits题1:Rule 90module top_module( input clk, input load, input [511:0] data, output [511:0] q ); integer i; always@(posedge clk)begin if(load) q<=data; el原创 2021-04-21 16:07:36 · 170 阅读 · 0 评论 -
HDLBits练习-移位寄存器
HDLBits练习Circuits-Seqential Logic-Shift Registes题1:4-bit shift registermodule top_module( input clk, input areset, // async active-high reset to zero input load, input ena, input [3:0] data, output reg [3:0] q); always@(pos原创 2021-04-21 14:11:16 · 141 阅读 · 0 评论