问题:枕头检测,frame_head来脉冲的同时din会来数据,连续三次数据都是8‘h23的话就输出一个脉冲。
比较懵的点是(frame_head)是一个单bit的标志脉冲(标志数据开始有效)?还是类似于数据的有效信号?
假定为类似数据的有效信号。
这个题目让我来做的话,我先会这样写(不考虑资源消耗)
module frame(
input clk,
input rst_n,
input frame_head,
input [7:0] din,
output detect
);
reg [23:0] temp_data;
always @ (posedge clk or negedge rst_n) begin
if(!rst_n) begin
temp_data <= 24'd0;
end
else if(frame_head) begin
temp_data <= {temp_data[15:0],din};
end
end
assign detect = (temp_data[23:0]==25'h232323) ? 1'b1 : 1'b0;
endmodule
这个的话,就是有个问题,会导致如果连续是4个有效的8’h23的话,就会产生2个脉冲的detect信号。所以我觉得应该是这样的,检测到3个有效8’h23之后,不会在之前的基础上检测3个有效的8’h23.这样的话,代码应该是下面这样。
module frame(
input clk,
input rst_n,
input frame_head,
input [7:0] din,
output reg detect
);
reg [1:0] cnt;
//reg [7:0] data_temp;
always @ (posedge clk or negedge rst_n) begin
if(!rst_n) begin
cnt <= 2'd0;
end
else if(frame_head && (din==8'h23)) begin
cnt <= cnt + 1'b1;
end
else if(frame_head && (din!=8'h23)) begin
cnt <= 2'd0;
end
else if(cnt==2'd3) begin
cnt <= 2'd0;
end
end
always @ (posedge clk or negedge rst_n) begin
if(!rst_n) begin
detect <= 1'b0;
end
else if(cnt==2'd3) begin
detect <= 1'b1;
end
else begin
detect <= 1'b0;
end
end
endmodule
接下来用状态机实现下这个功能
module frame(
input clk,
input rst_n,
input frame_head,
input [7:0] din,
output reg detect
);
reg [1:0] c_state;
reg [1:0] n_state;
always @ (posedge clk or negedge rst_n) begin
if(!rst_n) begin
c_state <= 2'd0;
end
else begin
c_state <= n_state;
end
end
always @ (*) begin
if(!rst_n) begin
n_state = 2'd0;
end
else if(frame_head) begin
case(c_state)
2'd0 : begin
if(din==8'h23) begin
n_state = 2'd1;
end
else begin
n_state = 2'd0;
end
end
2'd1 : begin
if(din==8'h23) begin
n_state = 2'd2;
end
else begin
n_state = 2'd0;
end
end
2'd2 : begin
if(din==8'h23) begin
n_state = 2'd0;
end
else begin
n_state = 2'd0;
end
end
default : n_state = 2'd0;
endcase
end
end
always @ (posedge clk or negedge rst_n) begin
if(!rst_n) begin
detect <= 1'b0;
end
else if(c_state==2'd2 && din ==8'h23 && frame_head) begin
detect <= 1'b1;
end
else begin
detect <= 1'b0;
end
end
endmodule