rk3568 Android13 rtl8211f qsgmii模式调试

DTS 除了配置 gmac 和 mac phy 节点外，还需要配置 xpcs 和 combophy 节点。combophy

其中属性 rockchip,sgmii-mac-sel 表示使用的是哪个 gmac：

&combphy1_usq {
+ rockchip,sgmii-mac-sel = <0>; /* Use gmac0 for sgmii */
status = "okay";
};

&xpcs {
status = "okay";
};

&gmac0 {
phy-mode = "sgmii";
rockchip,pipegrf = <&pipegrf>;
&gmac0 {
phy-mode = "sgmii";
rockchip,pipegrf = <&pipegrf>;
rockchip,xpcs = <&xpcs>;
snps,reset-gpio = <&gpio2 RK_PC2 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
snps,reset-delays-us = <0 20000 100000>;
assigned-clocks = <&cru SCLK_GMAC0_RX_TX>;
assigned-clock-parents = <&gmac0_xpcsclk>;
pinctrl-names = "default";
pinctrl-0 = <&gmac0_miim>;
power-domains = <&power RK3568_PD_PIPE>;
phys = <&combphy1_usq PHY_TYPE_SGMII>;
phy-handle = <&sgmii_phy>;
status = "okay";
};
&mdio0 {
sgmii_phy: phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x1>;
};
};
&gmac1 {
phy-mode = "sgmii";
rockchip,pipegrf = <&pipegrf>;
rockchip,xpcs = <&xpcs>;
snps,reset-gpio = <&gpio2 RK_PC2 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
snps,reset-delays-us = <0 20000 100000>;
assigned-clocks = <&cru SCLK_GMAC1_RX_TX>;
assigned-clock-parents = <&gmac1_xpcsclk>;
pinctrl-names = "default";
pinctrl-0 = <&gmac1_miim>;
power-domains = <&power RK3568_PD_PIPE>;
phys = <&combphy1_usq PHY_TYPE_SGMII>;
phy-handle = <&sgmii_phy>;
status = "okay";
};
&mdio1 {
sgmii_phy: phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x1>;
};
};

同 SGMIIl 类似，DTS 除了配置 gmac 和 mac phy 节点外，还需要配置 xpcs 和 combophy 节点。

combophy

&combphy2_psq {
status = "okay";
};

&xpcs {
status = "okay";
};

&gmac0 {
phy-supply = <&pcie20_3v3>;
phy-mode = "qsgmii";
rockchip,xpcs = <&xpcs>;
snps,reset-gpio = <&gpio2 RK_PC2 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
snps,reset-delays-us = <0 20000 100000>;
assigned-clocks = <&cru SCLK_GMAC0_RX_TX>;
assigned-clock-parents = <&gmac0_xpcsclk>;
pinctrl-names = "default";
pinctrl-0 = <&gmac0_miim>;
power-domains = <&power RK3568_PD_PIPE>;
phys = <&combphy2_psq PHY_TYPE_QSGMII>;
phy-handle = <&qsgmii_phy0>;
status = "okay";
};
&gmac1 {
phy-supply = <&pcie20_3v3>;
phy-mode = "qsgmii";
assigned-clocks = <&cru SCLK_GMAC1_RX_TX>;
assigned-clock-parents = <&gmac1_xpcsclk>;
power-domains = <&power RK3568_PD_PIPE>;
phy-handle = <&qsgmii_phy1>;
status = "okay";
};
&mdio0 {
qsgmii_phy0: phy@0 {
compatible = "ethernet-phy-id001c.c942", "ethernet-phy-ieee802.3-c22";
reg = <0x0>;
};
qsgmii_phy1: phy@1 {
compatible = "ethernet-phy-id001c.c942", "ethernet-phy-ieee802.3-c22";
reg = <0x1>;
};
qsgmii_phy2: phy@2 {
compatible = "ethernet-phy-id001c.c942", "ethernet-phy-ieee802.3-c22";
reg = <0x2>;
};
qsgmii_phy3: phy@3 {
compatible = "ethernet-phy-id001c.c942", "ethernet-phy-ieee802.3-c22";
reg = <0x3>;
};
};