好久之前写的,先发出来,以后有时间再写。
1.启动文件.S
内包含所有的中断函数,以及将程序跳转至主函数。这里的中断函数全是weak,一般外部重新定义
1.1 中断向量
9个故障处理中断+1个重置Reset+107个外设中断+1个堆载指针
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_IRQHandler ; PVD through EXTI Line detection
DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
DCD FLASH_IRQHandler ; FLASH
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line0
DCD EXTI1_IRQHandler ; EXTI Line1
;在此省略部分内容
DCD CAN3_RX1_IRQHandler ; CAN3 RX1
DCD CAN3_SCE_IRQHandler ; CAN3 SCE
DCD JPEG_IRQHandler ; JPEG
DCD MDIOS_IRQHandler ; MDIOS
__Vectors_End
中断 | 定义文件 | 注释 |
---|---|---|
9个故障处理中断 | stm32f7xx_it.c | 这个文件内的9个故障处理函数默认是空的,107个外部中断也可写在这里面。 |
107个外部中断 | 需要的时候再编写 |
2.基本配置文件
2.1 stm32f7xx_it.c
相对应的由stm32f7xx_it.h
理论上,是用来编写所有中断函数而创建,但在实际使用中,多直接单独创建一个文件编写。
it----interupt简称
引入的.h文件 | 包含内容 |
---|---|
“main.h” | 空 |
stm32f7xx_it.h | 中断函数的声明 |
2.2 stm32f7xx.h
只有.h文件,没有对应的.c文件
该文件是应用程序员唯一的包含文件
- 在 C 源代码中使用,通常在 main.c 中。 该文件包含:
- 允许选择的配置部分:
- 目标应用中使用的 STM32F7xx 器件
- 在应用程序代码中使用或不使用外设的驱动程序(即代码将基于对外设寄存器的直接访问而不是驱动程序 API),此选项由 “#define USE_HAL_DRIVER”
该部分文件进行了几个宏定义,但在实际使用中,我们是在编辑工具栏中进行的宏定义,就将这部分的代码注释了。几个宏定义如下(针对stm32f767xx的板子)
宏定义 | 功用 |
---|---|
STM32F7 | |
STM32F767XX | 如果定义了,则include stm32f767xx.h 文件 |
USE_HAL_DRIVER | 使用HAL库的标志–>如果定义,则include stm32f7xx_hal_conf.h |
|其余的宏定义(相当于函数)|
#define SET_BIT(REG, BIT) ((REG) |= (BIT))
#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
#define READ_BIT(REG, BIT) ((REG) & (BIT))
#define CLEAR_REG(REG) ((REG) = (0x0))
#define WRITE_REG(REG, VAL) ((REG) = (VAL))
#define READ_REG(REG) ((REG))
#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
|通用枚举类型|
typedef enum
{
RESET = 0,
SET = !RESET
} FlagStatus, ITStatus;
typedef enum
{
DISABLE = 0,
ENABLE = !DISABLE
} FunctionalState;
/*这里有一个宏定义函数*/
#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
typedef enum
{
ERROR = 0,
SUCCESS = !ERROR
} ErrorStatus;
还有一串暂时没搞懂的,看上面的英文应该是CMSIS版本存储进寄存器,但不知道这个有什么用??
——找到了一篇参考
/**
* @brief CMSIS Device version number V1.1.0
*/
#define __STM32F7_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */
#define __STM32F7_CMSIS_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */
#define __STM32F7_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32F7_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F7_CMSIS_VERSION ((__STM32F7_CMSIS_VERSION_MAIN << 24)\
|(__STM32F7_CMSIS_VERSION_SUB1 << 16)\
|(__STM32F7_CMSIS_VERSION_SUB2 << 8 )\
|(__STM32F7_CMSIS_VERSION))
/**
* @}
*/
2.3 stm32f767xx.h
只有头文件,没有对应的c文件
该文件包含:
- 所有外围设备的数据结构和地址映射
- 外围设备寄存器声明和位定义
- 访问外围设备寄存器硬件的宏
2.3.1 include 文件:
1)core_cm7.h
2)system_stm32f7xx.h
3)<stdint.h>
2.3.2 中断号定义,1个枚举类型
typedef enum
{
/****** Cortex-M7 Processor Exceptions Numbers ****************************************************************/
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
MemoryManagement_IRQn = -12, /*!< 4 Cortex-M7 Memory Management Interrupt */
BusFault_IRQn = -11, /*!< 5 Cortex-M7 Bus Fault Interrupt */
UsageFault_IRQn = -10, /*!< 6 Cortex-M7 Usage Fault Interrupt */
SVCall_IRQn = -5, /*!< 11 Cortex-M7 SV Call Interrupt */
DebugMonitor_IRQn = -4, /*!< 12 Cortex-M7 Debug Monitor Interrupt */
PendSV_IRQn = -2, /*!< 14 Cortex-M7 Pend SV Interrupt */
SysTick_IRQn = -1, /*!< 15 Cortex-M7 System Tick Interrupt */
/****** STM32 specific Interrupt Numbers **********************************************************************/
WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
FLASH_IRQn = 4, /*!< FLASH global Interrupt */
RCC_IRQn = 5, /*!< RCC global Interrupt */
EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
/****在此省略部分***/
JPEG_IRQn = 108, /*!< JPEG global Interrupt */
MDIOS_IRQn = 109 /*!< MDIO Slave global Interrupt */
} IRQn_Type;
2.3.3 Cortex-M7 处理器和内核外设的配置
#define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */
#define __MPU_PRESENT 1 /*!< CM7 provides an MPU */
#define __NVIC_PRIO_BITS 4 /*!< CM7 uses 4 Bits for the Priority Levels */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
#define __FPU_PRESENT 1 /*!< FPU present */
#define __ICACHE_PRESENT 1 /*!< CM7 instruction cache present */
#define __DCACHE_PRESENT 1 /*!< CM7 data cache present */
2.3.4 外设寄存器的结构体定义
example:
/**
* @brief Analog to Digital Converter
*/
typedef struct
{
__IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
__IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
__IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
__IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
__IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
__IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
__IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
__IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
__IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
__IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
__IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
__IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
__IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
__IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
__IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
__IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
__IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
__IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
__IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
__IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
} ADC_TypeDef;
typedef struct
{
__IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
__IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
__IO uint32_t CDR; /*!< ADC common regular data register for dual
AND triple modes, Address offset: ADC1 base address + 0x308 */
} ADC_Common_TypeDef;
(共53个?)
外设寄存器结构体列表 | 功用 | 包含结构体 |
---|---|---|
ADC_TypeDef | ||
ADC_Common_TypeDef | ||
CAN_TxMailBox_TypeDef | ||
CAN_FIFOMailBox_TypeDef | Controller Area Network FIFOMailBox | |
CAN_FilterRegister_TypeDef | Controller Area Network FilterRegister | |
CAN_TypeDef | Controller Area Network | 内部套用了前三个结构体CAN_TxMailBox_TypeDef、CAN_FIFOMailBox_TypeDef、CAN_FilterRegister_TypeDef |
CEC_TypeDef | HDMI-CEC | |
CRC_TypeDef | CRC calculation unit | |
DAC_TypeDef | Digital to Analog Converter | |
DFSDM_Filter_TypeDef | DFSDM module registers | |
DFSDM_Channel_TypeDef | DFSDM channel configuration registers | |
DBGMCU_TypeDef | Debug MCU | |
DCMI_TypeDef | DCMI | |
DMA_Stream_TypeDef | DMA Controller | |
DMA_TypeDef | 同上 | |
DMA2D_TypeDef | DMA2D Controller | |
ETH_TypeDef | Ethernet MAC | |
EXTI_TypeDef | External Interrupt/Event Controller | |
FLASH_TypeDef | FLASH Registers | |
FMC_Bank1_TypeDef | Flexible Memory Controller | |
FMC_Bank1E_TypeDef | Flexible Memory Controller Bank1E | |
FMC_Bank3_TypeDef | Flexible Memory Controller Bank3 | |
FMC_Bank5_6_TypeDef | Flexible Memory Controller Bank5_6 | |
GPIO_TypeDef | General Purpose I/O | |
SYSCFG_TypeDef | System configuration controller | |
I2C_TypeDef | Inter-integrated Circuit Interface | |
IWDG_TypeDef | Independent WATCHDOG | |
LTDC_TypeDef | LCD-TFT Display Controller | |
LTDC_Layer_TypeDef | LCD-TFT Display layer x Controller | |
PWR_TypeDef | Power Control | |
RCC_TypeDef | Reset and Clock Control | |
RTC_TypeDef | Real-Time Clock | |
SAI_TypeDef | Serial Audio Interface | |
SAI_Block_TypeDef | 同上 | |
SPDIFRX_TypeDef | SPDIF-RX Interface | |
SDMMC_TypeDef | SD host Interface | |
SPI_TypeDef | Serial Peripheral Interface | |
QUADSPI_TypeDef | QUAD Serial Peripheral Interface | |
TIM_TypeDef | TIM | |
LPTIM_TypeDef | LPTIMIMER | |
USART_TypeDef | Universal Synchronous Asynchronous Receiver Transmitter | |
WWDG_TypeDef | Window WATCHDOG | |
RNG_TypeDef | RNG | |
USB_OTG_GlobalTypeDef | USB_OTG_Core_Registers | |
USB_OTG_DeviceTypeDef | USB_OTG_device_Registers | |
USB_OTG_INEndpointTypeDef | USB_OTG_IN_Endpoint-Specific_Register | |
USB_OTG_OUTEndpointTypeDef | USB_OTG_OUT_Endpoint-Specific_Registers | |
USB_OTG_HostTypeDef | USB_OTG_Host_Mode_Register_Structures | |
USB_OTG_HostChannelTypeDef | USB_OTG_Host_Channel_Specific_Registers | |
JPEG_TypeDef | JPEG Codec | |
MDIOS_TypeDef | MDIOS |
2.3.5 外设基地址(Peripheral_memory_map)
12+9
12项基本+9项地址迭代
#define RAMITCM_BASE 0x00000000U /*!< Base address of : 16KB RAM reserved for CPU execution/instruction accessible over ITCM */
#define FLASHITCM_BASE 0x00200000U /*!< Base address of : (up to 2 MB) embedded FLASH memory accessible over ITCM */
#define FLASHAXI_BASE 0x08000000U /*!< Base address of : (up to 2 MB) embedded FLASH memory accessible over AXI */
#define RAMDTCM_BASE 0x20000000U /*!< Base address of : 128KB system data RAM accessible over DTCM */
#define PERIPH_BASE 0x40000000U /*!< Base address of : AHB/ABP Peripherals */
#define BKPSRAM_BASE 0x40024000U /*!< Base address of : Backup SRAM(4 KB) */
#define QSPI_BASE 0x90000000U /*!< Base address of : QSPI memories accessible over AXI */
#define FMC_R_BASE 0xA0000000U /*!< Base address of : FMC Control registers */
#define QSPI_R_BASE 0xA0001000U /*!< Base address of : QSPI Control registers */
#define SRAM1_BASE 0x20020000U /*!< Base address of : 368KB RAM1 accessible over AXI/AHB */
#define SRAM2_BASE 0x2007C000U /*!< Base address of : 16KB RAM2 accessible over AXI/AHB */
#define FLASH_END 0x081FFFFFU /*!< FLASH end address */
/* Legacy define */
#define FLASH_BASE FLASHAXI_BASE
/*!< Peripheral memory map */
#define APB1PERIPH_BASE PERIPH_BASE
#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U)
/*!< APB1 peripherals */
#define TIM2_BASE (APB1PERIPH_BASE + 0x0000U)
#define TIM3_BASE (APB1PERIPH_BASE + 0x0400U)
#define TIM4_BASE (APB1PERIPH_BASE + 0x0800U)
/* 省略部分 */
/*!< APB2 peripherals */
#define TIM1_BASE (APB2PERIPH_BASE + 0x0000U)
#define TIM8_BASE (APB2PERIPH_BASE + 0x0400U)
/* 省略部分 */
/*!< AHB1 peripherals */
#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)
#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)
/* 省略部分 */
/*!< AHB2 peripherals */
#define DCMI_BASE (AHB2PERIPH_BASE + 0x50000U)
#define JPEG_BASE (AHB2PERIPH_BASE + 0x51000U)
#define RNG_BASE (AHB2PERIPH_BASE + 0x60800U)
/*!< FMC Bankx registers base address */
#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000U)
#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104U)
#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080U)
#define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140U)
/* Debug MCU registers base address */
#define DBGMCU_BASE 0xE0042000U
/*!< USB registers base address */
#define USB_OTG_HS_PERIPH_BASE 0x40040000U
#define USB_OTG_FS_PERIPH_BASE 0x50000000U
#define USB_OTG_GLOBAL_BASE 0x000U
#define USB_OTG_DEVICE_BASE 0x800U
#define USB_OTG_IN_ENDPOINT_BASE 0x900U
/* 省略部分 */
#define USB_OTG_FIFO_SIZE 0x1000U
2.3.6 Peripheral_declaration外设声明
以2.3.5中的基地址为首,定义2.3.4中的结构体指针,示例如下:
#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
TIM2_BASE是外设TIM2寄存器的基地址,结构体TIM_TypeDef定义该寄存器的各个位。定义为结构体指针是为了实现更便捷的访问?
2.3.7 外设寄存器的位定义
是将某些常用的寄存器组合设置了宏定义,在对寄存器的位幅值时,可以使用这里的宏定义,也可直接赋予需要的数值。
即这部分不是必要的,只是为了更便捷的操作,代码也有很强的可读性,能够通过宏定义的名称一目了然的理解这个位赋予的功能。
相对的,如果直接幅值,则需要查对应的手册,查看幅值的含义。
/**示例**/
/******************** Bit definition for MDIOS_SR register *******************/
#define MDIOS_SR_PERF 0x00000001U /*!< Preamble error flag */
#define MDIOS_SR_SERF 0x00000002U /*!< Start error flag */
#define MDIOS_SR_TERF 0x00000004U /*!< Turnaround error flag */
2.3.8 导出宏 Exported_macros
这部分设置了一些常用的宏操作,相当于用宏定义写了一个简单的函数
/******************************* ADC Instances ********************************/
#define IS_ADC_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == ADC1) || \
((__INSTANCE__) == ADC2) || \
((__INSTANCE__) == ADC3))
2.4 core_cm7.h
内核的寄存器结构体和位定义?
#include <stdint.h>
#include “core_cmInstr.h” /* Core Instruction Access /
#include “core_cmFunc.h” / Core Function Access /
#include “core_cmSimd.h” / Compiler specific SIMD Intrinsics */
2.5 system_stm32f7xx.c
#include “stm32f7xx.h”----有函数申明
该.c文件主要是设置单片机的时钟
2.6 stm32f7xx_hal.c
#include “stm32f7xx_hal_conf.h” —>该文件是hal库的一些基本设置,且包含了所有hal库C文件对应的H文件。