【verilog】如何使用verilog写一个秒表

最新推荐文章于 2024-08-10 11:26:56 发布
最新推荐文章于 2024-08-10 11:26:56 发布
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设计要求如上图所示在这里插入图片描述

其实要实现这题的功能很简单，就是一个简单的映射关系，话不多说，直接上代码！

代码如下所示

// An highlighted block
module stopwatch(
	input clk,
	input rst_n,

	input timer_start,
	input timer_stop,

	output [5:0] light_a,
	output [5:0] light_b,
	output [5:0] light_c,
	output [5:0] light_d,
	output [5:0] light_e,
	output [5:0] light_f,
	output [5:0] light_g,
	output [1:0] light_dp
);
logic [5:0] light_a;
logic [5:0] light_b;
logic [5:0] light_c;
logic [5:0] light_d;
logic [5:0] light_e;
logic [5:0] light_f;
logic [5:0] light_g;
logic [1:0] light_dp;

logic [3:0] hh_l;
logic [3:0] hh_h;
logic [3:0] mm_l;
logic [3:0] mm_h;
logic [3:0] ss_l;
logic [3:0] ss_h;

logic [3:0] clk_cnt;
logic [5:0] s_cnt;
logic [5:0] m_cnt;
logic [6:0] h_cnt;

logic timer_stop_en;
logic timer_start_en;

always@(posedge clk or negedge rst_n) begin
	if(!rst_n) begin
		timer_stop_en <= 0;
		timer_start_en <= 0;
	end
	else if(timer_stop) begin
		timer_stop_en <= 1;
		timer_start_en <= 0;
	end
	else if(timer_start) begin
		timer_stop_en <= 0;
		timer_start_en <= 1;
	end
end

always@(posedge clk or negedge rst_n) begin
	if(!rst_n) 
		clk_cnt <= 0;
	else if(timer_stop_en) begin
		clk_cnt <= clk_cnt;
	end
	else if(timer_start_en) begin
		if(clk_cnt == 9) clk_cnt <= 0;
		else clk_cnt <= clk_cnt + 1;
	end
end
always@(posedge clk or negedge rst_n) begin
	if(!rst_n) 
		s_cnt <= 0;
	else if(timer_stop_en) 
		s_cnt <= s_cnt;
	else if(timer_start_en) begin
		if(clk_cnt == 9 && s_cnt == 59) s_cnt <= 0;
		else if(clk_cnt == 9) s_cnt <= s_cnt + 1;
		else s_cnt <= s_cnt;
	end
end
always@(posedge clk or negedge rst_n) begin
	if(!rst_n) 
		m_cnt <= 0;
	else if(timer_stop_en) 
		m_cnt <= m_cnt;
	else if(timer_start_en) begin
		if(clk_cnt == 9 && s_cnt == 59 && m_cnt == 59) m_cnt <= 0;
		else if(clk_cnt == 9 && s_cnt == 59) m_cnt <= m_cnt + 1;
		else m_cnt <= m_cnt;
	end
end
always@(posedge clk or negedge rst_n) begin
	if(!rst_n) 
		h_cnt <= 0;
	else if(timer_stop_en) 
		h_cnt <= h_cnt;
	else if(timer_start_en) begin
		if(clk_cnt == 9 && s_cnt == 59 && m_cnt == 59 && h_cnt == 99) h_cnt <= 0;
		else if(clk_cnt == 9 && s_cnt == 59 && m_cnt == 59) h_cnt <= h_cnt + 1;
		else h_cnt <= h_cnt;
	end
end
always@(*) begin
	case(s_cnt % 10)
		0:beigin light_a[0] = 1; light_b[0] = 1; light_c[0] = 1; light_d[0] = 1; light_e[0] = 1; light_f[0] = 1; light_g[0] = 0;end
		1:beigin light_a[0] = 0; light_b[0] = 1; light_c[0] = 1; light_d[0] = 0; light_e[0] = 0; light_f[0] = 0; light_g[0] = 0;end
		2:beigin light_a[0] = 1; light_b[0] = 1; light_c[0] = 0; light_d[0] = 1; light_e[0] = 1; light_f[0] = 0; light_g[0] = 1;end
		3:beigin light_a[0] = 1; light_b[0] = 1; light_c[0] = 1; light_d[0] = 1; light_e[0] = 0; light_f[0] = 0; light_g[0] = 1;end
		4:beigin light_a[0] = 0; light_b[0] = 1; light_c[0] = 1; light_d[0] = 0; light_e[0] = 0; light_f[0] = 1; light_g[0] = 1;end
		5:beigin light_a[0] = 1; light_b[0] = 0; light_c[0] = 1; light_d[0] = 1; light_e[0] = 0; light_f[0] = 1; light_g[0] = 1;end
		6:beigin light_a[0] = 1; light_b[0] = 0; light_c[0] = 1; light_d[0] = 1; light_e[0] = 1; light_f[0] = 1; light_g[0] = 1;end
		7:beigin light_a[0] = 1; light_b[0] = 1; light_c[0] = 1; light_d[0] = 0; light_e[0] = 0; light_f[0] = 0; light_g[0] = 0;end
		8:beigin light_a[0] = 1; light_b[0] = 1; light_c[0] = 1; light_d[0] = 1; light_e[0] = 1; light_f[0] = 1; light_g[0] = 1;end
		9:beigin light_a[0] = 1; light_b[0] = 1; light_c[0] = 1; light_d[0] = 1; light_e[0] = 0; light_f[0] = 1; light_g[0] = 1;end
		default:beigin light_a[0] = 1; light_b[0] = 1; light_c[0] = 1; light_d[0] = 1; light_e[0] = 1; light_f[0] = 1; light_g[0] = 0;end
	endcase
end
always@(*) begin
	case(s_cnt / 10)
		0:beigin light_a[1] = 1; light_b[1] = 1; light_c[1] = 1; light_d[1] = 1; light_e[1] = 1; light_f[1] = 1; light_g[1] = 0;end
		1:beigin light_a[1] = 0; light_b[1] = 1; light_c[1] = 1; light_d[1] = 0; light_e[1] = 0; light_f[1] = 0; light_g[1] = 0;end
		2:beigin light_a[1] = 1; light_b[1] = 1; light_c[1] = 0; light_d[1] = 1; light_e[1] = 1; light_f[1] = 0; light_g[1] = 1;end
		3:beigin light_a[1] = 1; light_b[1] = 1; light_c[1] = 1; light_d[1] = 1; light_e[1] = 0; light_f[1] = 0; light_g[1] = 1;end
		4:beigin light_a[1] = 0; light_b[1] = 1; light_c[1] = 1; light_d[1] = 0; light_e[1] = 0; light_f[1] = 1; light_g[1] = 1;end
		5:beigin light_a[1] = 1; light_b[1] = 0; light_c[1] = 1; light_d[1] = 1; light_e[1] = 0; light_f[1] = 1; light_g[1] = 1;end
		6:beigin light_a[1] = 1; light_b[1] = 0; light_c[1] = 1; light_d[1] = 1; light_e[1] = 1; light_f[1] = 1; light_g[1] = 1;end
		7:beigin light_a[1] = 1; light_b[1] = 1; light_c[1] = 1; light_d[1] = 0; light_e[1] = 0; light_f[1] = 0; light_g[1] = 0;end
		8:beigin light_a[1] = 1; light_b[1] = 1; light_c[1] = 1; light_d[1] = 1; light_e[1] = 1; light_f[1] = 1; light_g[1] = 1;end
		9:beigin light_a[1] = 1; light_b[1] = 1; light_c[1] = 1; light_d[1] = 1; light_e[1] = 0; light_f[1] = 1; light_g[1] = 1;end
		default:beigin light_a[1] = 1; light_b[1] = 1; light_c[1] = 1; light_d[1] = 1; light_e[1] = 1; light_f[1] = 1; light_g[1] = 0;end
	endcase
end
always@(*) begin
	case(m_cnt % 10)
		0:beigin light_a[2] = 1; light_b[2] = 1; light_c[2] = 1; light_d[2] = 1; light_e[2] = 1; light_f[2] = 1; light_g[2] = 0;end
		1:beigin light_a[2] = 0; light_b[2] = 1; light_c[2] = 1; light_d[2] = 0; light_e[2] = 0; light_f[2] = 0; light_g[2] = 0;end
		2:beigin light_a[2] = 1; light_b[2] = 1; light_c[2] = 0; light_d[2] = 1; light_e[2] = 1; light_f[2] = 0; light_g[2] = 1;end
		3:beigin light_a[2] = 1; light_b[2] = 1; light_c[2] = 1; light_d[2] = 1; light_e[2] = 0; light_f[2] = 0; light_g[2] = 1;end
		4:beigin light_a[2] = 0; light_b[2] = 1; light_c[2] = 1; light_d[2] = 0; light_e[2] = 0; light_f[2] = 1; light_g[2] = 1;end
		5:beigin light_a[2] = 1; light_b[2] = 0; light_c[2] = 1; light_d[2] = 1; light_e[2] = 0; light_f[2] = 1; light_g[2] = 1;end
		6:beigin light_a[2] = 1; light_b[2] = 0; light_c[2] = 1; light_d[2] = 1; light_e[2] = 1; light_f[2] = 1; light_g[2] = 1;end
		7:beigin light_a[2] = 1; light_b[2] = 1; light_c[2] = 1; light_d[2] = 0; light_e[2] = 0; light_f[2] = 0; light_g[2] = 0;end
		8:beigin light_a[2] = 1; light_b[2] = 1; light_c[2] = 1; light_d[2] = 1; light_e[2] = 1; light_f[2] = 1; light_g[2] = 1;end
		9:beigin light_a[2] = 1; light_b[2] = 1; light_c[2] = 1; light_d[2] = 1; light_e[2] = 0; light_f[2] = 1; light_g[2] = 1;end
		default:beigin light_a[2] = 1; light_b[2] = 1; light_c[2] = 1; light_d[2] = 1; light_e[2] = 1; light_f[2] = 1; light_g[2] = 0;end
	endcase
end
always@(*) begin
	case(m_cnt / 10)
		0:beigin light_a[3] = 1; light_b[3] = 1; light_c[3] = 1; light_d[3] = 1; light_e[3] = 1; light_f[3] = 1; light_g[3] = 0;end
		1:beigin light_a[3] = 0; light_b[3] = 1; light_c[3] = 1; light_d[3] = 0; light_e[3] = 0; light_f[3] = 0; light_g[3] = 0;end
		2:beigin light_a[3] = 1; light_b[3] = 1; light_c[3] = 0; light_d[3] = 1; light_e[3] = 1; light_f[3] = 0; light_g[3] = 1;end
		3:beigin light_a[3] = 1; light_b[3] = 1; light_c[3] = 1; light_d[3] = 1; light_e[3] = 0; light_f[3] = 0; light_g[3] = 1;end
		4:beigin light_a[3] = 0; light_b[3] = 1; light_c[3] = 1; light_d[3] = 0; light_e[3] = 0; light_f[3] = 1; light_g[3] = 1;end
		5:beigin light_a[3] = 1; light_b[3] = 0; light_c[3] = 1; light_d[3] = 1; light_e[3] = 0; light_f[3] = 1; light_g[3] = 1;end
		6:beigin light_a[3] = 1; light_b[3] = 0; light_c[3] = 1; light_d[3] = 1; light_e[3] = 1; light_f[3] = 1; light_g[3] = 1;end
		7:beigin light_a[3] = 1; light_b[3] = 1; light_c[3] = 1; light_d[3] = 0; light_e[3] = 0; light_f[3] = 0; light_g[3] = 0;end
		8:beigin light_a[3] = 1; light_b[3] = 1; light_c[3] = 1; light_d[3] = 1; light_e[3] = 1; light_f[3] = 1; light_g[3] = 1;end
		9:beigin light_a[3] = 1; light_b[3] = 1; light_c[3] = 1; light_d[3] = 1; light_e[3] = 0; light_f[3] = 1; light_g[3] = 1;end
		default:beigin light_a[3] = 1; light_b[3] = 1; light_c[3] = 1; light_d[3] = 1; light_e[3] = 1; light_f[3] = 1; light_g[3] = 0;end
	endcase
end
always@(*) begin
	case(h_cnt % 10)
		0:beigin light_a[4] = 1; light_b[4] = 1; light_c[4] = 1; light_d[4] = 1; light_e[4] = 1; light_f[4] = 1; light_g[4] = 0;end
		1:beigin light_a[4] = 0; light_b[4] = 1; light_c[4] = 1; light_d[4] = 0; light_e[4] = 0; light_f[4] = 0; light_g[4] = 0;end
		2:beigin light_a[4] = 1; light_b[4] = 1; light_c[4] = 0; light_d[4] = 1; light_e[4] = 1; light_f[4] = 0; light_g[4] = 1;end
		3:beigin light_a[4] = 1; light_b[4] = 1; light_c[4] = 1; light_d[4] = 1; light_e[4] = 0; light_f[4] = 0; light_g[4] = 1;end
		4:beigin light_a[4] = 0; light_b[4] = 1; light_c[4] = 1; light_d[4] = 0; light_e[4] = 0; light_f[4] = 1; light_g[4] = 1;end
		5:beigin light_a[4] = 1; light_b[4] = 0; light_c[4] = 1; light_d[4] = 1; light_e[4] = 0; light_f[4] = 1; light_g[4] = 1;end
		6:beigin light_a[4] = 1; light_b[4] = 0; light_c[4] = 1; light_d[4] = 1; light_e[4] = 1; light_f[4] = 1; light_g[4] = 1;end
		7:beigin light_a[4] = 1; light_b[4] = 1; light_c[4] = 1; light_d[4] = 0; light_e[4] = 0; light_f[4] = 0; light_g[4] = 0;end
		8:beigin light_a[4] = 1; light_b[4] = 1; light_c[4] = 1; light_d[4] = 1; light_e[4] = 1; light_f[4] = 1; light_g[4] = 1;end
		9:beigin light_a[4] = 1; light_b[4] = 1; light_c[4] = 1; light_d[4] = 1; light_e[4] = 0; light_f[4] = 1; light_g[4] = 1;end
		default:beigin light_a[4] = 1; light_b[4] = 1; light_c[4] = 1; light_d[4] = 1; light_e[4] = 1; light_f[4] = 1; light_g[4] = 0;end
	endcase
end
always@(*) begin
	case(h_cnt / 10)
		0:beigin light_a[5] = 1; light_b[5] = 1; light_c[5] = 1; light_d[5] = 1; light_e[5] = 1; light_f[5] = 1; light_g[5] = 0;end
		1:beigin light_a[5] = 0; light_b[5] = 1; light_c[5] = 1; light_d[5] = 0; light_e[5] = 0; light_f[5] = 0; light_g[5] = 0;end
		2:beigin light_a[5] = 1; light_b[5] = 1; light_c[5] = 0; light_d[5] = 1; light_e[5] = 1; light_f[5] = 0; light_g[5] = 1;end
		3:beigin light_a[5] = 1; light_b[5] = 1; light_c[5] = 1; light_d[5] = 1; light_e[5] = 0; light_f[5] = 0; light_g[5] = 1;end
		4:beigin light_a[5] = 0; light_b[5] = 1; light_c[5] = 1; light_d[5] = 0; light_e[5] = 0; light_f[5] = 1; light_g[5] = 1;end
		5:beigin light_a[5] = 1; light_b[5] = 0; light_c[5] = 1; light_d[5] = 1; light_e[5] = 0; light_f[5] = 1; light_g[5] = 1;end
		6:beigin light_a[5] = 1; light_b[5] = 0; light_c[5] = 1; light_d[5] = 1; light_e[5] = 1; light_f[5] = 1; light_g[5] = 1;end
		7:beigin light_a[5] = 1; light_b[5] = 1; light_c[5] = 1; light_d[5] = 0; light_e[5] = 0; light_f[5] = 0; light_g[5] = 0;end
		8:beigin light_a[5] = 1; light_b[5] = 1; light_c[5] = 1; light_d[5] = 1; light_e[5] = 1; light_f[5] = 1; light_g[5] = 1;end
		9:beigin light_a[5] = 1; light_b[5] = 1; light_c[5] = 1; light_d[5] = 1; light_e[5] = 0; light_f[5] = 1; light_g[5] = 1;end
		default:beigin light_a[5] = 1; light_b[5] = 1; light_c[5] = 1; light_d[5] = 1; light_e[5] = 1; light_f[5] = 1; light_g[5] = 0;end
	endcase
end
assign light_dp = 2'b11;
endmodule

这是较简单的写法来实现stopwatch功能，但是在实际过程中并不推荐使用除余%与除法/来实现，在时钟频率较高时可能会出现时序难以收敛，所以在下一篇中将会尝试用更好的写法来实现该功能。

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设计电子表，电子表指示的时间由nexys4 DDR开发板的8个数码管显示，从左到右数码管的前两个显示小时（范围0-24），第3-4个数码管显示分（范围0-59，计数到60，向小时位进1），第5-6个数码管显示秒（范围0-59，计数到60向分位进1），第7-8个数码管显示毫秒（范围0-99，计数到100向秒位进1） 。要求实现如下功能： (1)跑表的计时范围为0.01s~59min59.99s，计时精度为10ms。 (2)具有异步清零、启动功能。 (3)计时频率为100Hz。 (4)数字跑表的分和秒在数码管上显示出来，百分秒的BCD码在8个led上显示出来。
Verilog设计倒计时秒表
m0_57283507的博客
06-19 3513
通过NEXY4 DDR设计倒计时秒表
Verilog HDL的数字秒表设计
qq_44249640的博客
05-26 7362
目录一.介绍二.实验过程 一.介绍 1.Verilog HDL Verilog HDL是一种硬件描述语言，以文本形式来描述数字系统硬件的结构和行为的语言，用它可以表示逻辑电路图、逻辑表达式，还可以表示数字逻辑系统所完成的逻辑功能。 更多可以看：https://baike.baidu.com/item/Verilog%20HDL/596353?fr=aladdin 2.数字秒表设计 在发烧友上看到的原理图 二.实验过程 1.准备工作 （1）建立工程 （2）添加文件 如图选择Verilog 2.代码
【Verilog闯关第2天】数字秒表的设计
qq_39591444的博客
05-08 2620
数字秒表设计
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