Implementing Manchester and BMC encoder/decoder on EFM8LB1

本文介绍了如何在Silicon Labs的EFM8LB1上使用Configurable Logic Units (CLU) 实现曼彻斯特编码和Biphase Mark Code (BMC) 编解码。曼彻斯特编码是一种广泛应用于10BASE-T以太网的数据和时钟传输方法。而BMC利用边沿变化表示逻辑值。文章详细阐述了两种编码方式的编码和解码原理,并给出了具体的实现方案和波形图。

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Implementing Manchester and BMC encoder/decoder on EFM8LB1

1. Introduction

The Manchester code and Biphase Mark Code(BMC) are popular line code which conveys the data and clock information. Here will introduce how to implement Manchester and BMC encoder/decoder on Silicon Labs EFM8LB1 with its Configurable Logic Units(CLU).

2. Manchester code

Manchester Code is widely used(e.G., In 10BASE-T Ethernet(IEEE802.3)). The encoding of each bit is either low then high, or high then low, of equal time. For IEEE802.3 standard, “1” is represented by a rising edge. “0” is represented by a failing edge. It has no DC component, and is self-clocking.

MC Bit

Figure 1 Manchester Bit Data (IEEE802.3)

2.1. Manchester Encoder

It is easy to generate Manchester encoded data by XOR SPI MOSI and SCK signals. The SCK phase and polarity setting (CKPOL = 0, CKPHA = 1). the EFM8LB1 CLU setting to implement Manchester Encoder as follows.

MC Encoder

Figure 2 Manchester Encoder

The CLU configuration code as follows:

SFRPAGE = 0x20;
/* MXA as P0.4, MXB as P0.7*/
CLU0MX = 0xAB; 
CLU0FN = LUT_XOR(SI_LUT_A, SI_LUT_B); 
CLU0CF = CLU0CF_OEN__ENABLE |         CLU0CF_OUTSEL__LUT;
CLEN0 |= CLEN0_C0EN__ENABLE;
SFRPAGE = 0;

The Manchester Encoder waveform is shown as follows:

MC Encoder Waveform

Figure 3 Manchester Encoder Waveform

From the waveform, when MOSI = 0, the XORed output follows SCK, it is failing edge = ‘0’; When MOSI = 1, the XORed output is an inverted SCK, it is rising edge = ‘1’.

2.2. Manchester Decoder

The Manchester bit value is presented in the second half of each bit time. Here we can generate a clock to capture the value at second half of bit time. The transition in middle of each bit triggers timer with 3/8 bit time. Generating SCK rising edge when timer overflow. Generating SCK failing edge when timer overflow again and stop the timer. Repeat above steps for rest bits.

MC Decoder Clock

Figure 4 Manchester Decoder Clock Generation

How to trigger the Timer at Manchester middle transition? First, Generating latch data by capturing the data at 6/8 bit time. Second, Manchester data XOR latch data to get rising edge at

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