边沿检测

边沿检测

边沿检测模块代码

module edge_check( 
    input				clk		,
    input				rst_n	,
    input               signial ,//输入系统外部信号

    output	wire	        pos_edge,//上升沿检测输出标志
    output	wire 	        neg_edge	
);								  			 
                        
    //中间信号定义		 
    reg			signial_r;//输入信号寄存器

    always @(posedge clk or negedge rst_n)begin 
            if(rst_n == 1'b0)begin
                signial_r <= 0;
            end 
            else begin 
                signial_r <= signial;
            end 
    end

    //当外部输入signial 由1变0时，neg_edge为高电平，并维持一个时钟周期
    assign neg_edge = signial_r & (~signial);
    //当外部输入signial 由0变1时，pos_edge为高电平，并维持一个时钟周期
    assign pos_edge = (~signial_r) & signial;

endmodule

边沿检测测试模块

`timescale 1ns/1ns
                
module edge_check_tb();
//激励信号定义 
reg				tb_clk  	;
reg				tb_rst_n	;
reg				signial		;

//输出信号定义	 
wire	    	pos_edge	;
wire	    	neg_edge    ;
                                          
//时钟周期参数定义					        
parameter		CLOCK_CYCLE = 20    ;
                                          
edge_check u_edge_check( 
    .	clk		(tb_clk),
    .	rst_n	(tb_rst_n),
    .   signial (signial),//输入系统外部信号

    .   pos_edge(pos_edge),//上升沿检测输出标志
    .   neg_edge(neg_edge)	
);							
//产生时钟							       		
initial 		tb_clk = 1'b0;		       		
always #(CLOCK_CYCLE/2) tb_clk = ~tb_clk;  		
                                                   
//产生激励							       		
initial  begin						       		
    tb_rst_n = 1'b0;								
    signial = 1;								
    #(CLOCK_CYCLE*20);				            
    tb_rst_n = 1'b1;
    #200 	signial = 0;
    #200 	signial = 1;
    #200 	signial = 0;
    #200 	signial = 1; 
    #200 	signial = 0;
    #200 	signial = 1;
    #200 	signial = 0;                                              
    end							       			
                                                   
endmodule 				

rtl视图

仿真波形图