module top_module (
input clk,
input [7:0] in,
output [7:0] anyedge
);
reg [7:0] d_last;
always @(posedge clk) begin
d_last <= in; // Remember the state of the previous cycle
anyedge <= in ^ d_last; // A positive edge occurred if input was 0 and is now 1.
end
endmodule
https://hdlbits.01xz.net/wiki/Edgedetect2
可以直接将组合逻辑放在两个DFF之间,精简代码和资源。
边沿检测电路(edge detection circuit)是个常用的基本电路。
所谓边沿检测就是对前一个clock状态和目前clock状态的比较,如果是由0变为1,能够检测到上升沿,则称为上升沿检测电路(posedge edge detection circuit),若是由1变为0,能够检测到下降沿,则被称为下降沿检测电路(negedge edge dttection circuit),能够同时检测