HDLBits刷题（电路-组合逻辑-多路选择器和算术电路）

2-to-1 multiplexer/2-to-1 bus multiplexer

module top_module( 
    input a, b, sel,
    output out ); 
assign out=sel?b:a;
endmodule

9-to-1 multiplexer

module top_module( 
    input [15:0] a, b, c, d, e, f, g, h, i,
    input [3:0] sel,
    output [15:0] out );
    always@(*)
        case(sel)
            4'h0:out=a;
            4'h1:out=b;
            4'h2:out=c;
            4'h3:out=d;
            4'h4:out=e;
            4'h5:out=f;
            4'h6:out=g;
            4'h7:out=h;
            4'h8:out=i;
            default:out=16'hffff;
        endcase
endmodule

256-to-1 multiplexer

module top_module( 
    input [255:0] in,
    input [7:0] sel,
    output out );
    assign out=in[sel];
endmodule

256-to-1 4-bit multiplexer

module top_module( 
    input [1023:0] in,
    input [7:0] sel,
    output [3:0] out );
    assign out=in[sel*4+:4];
endmodule

Half adder

module top_module( 
    input a, b,
    output cout, sum );
    assign {cout,sum}=a+b;
endmodule

Full adder

module top_module( 
    input a, b, cin,
    output cout, sum );
    assign {cout,sum}=a+b+cin;
endmodule

3-bit binary adder 

module top_module( 
    input [2:0] a, b,
    input cin,
    output [2:0] cout,
    output [2:0] sum );
    assign {cout[0],sum[0]}=a[0]+b[0]+cin;
    assign {cout[1],sum[1]}=a[1]+b[1]+cout[0];
    assign {cout[2],sum[2]}=a[2]+b[2]+cout[1];
endmodule

Adder

module top_module (
    input [3:0] x,
    input [3:0] y, 
    output [4:0] sum);
assign sum=x+y;
endmodule

Signer additon overflow

module top_module (
    input [7:0] a,
    input [7:0] b,
    output [7:0] s,
    output overflow
);
    assign s = a+b;
    assign overflow =(a[7]&b[7]&~s[7])||(~a[7]&~b[7]&s[7]);
endmodule

100-bit binary adder 

module top_module( 
    input [99:0] a, b,
    input cin,
    output cout,
    output [99:0] sum );
assign {cout,sum}=a+b+cin;
endmodule

4 digit BCD adder

module top_module ( 
    input [15:0] a, b,
    input cin,
    output cout,
    output [15:0] sum );
    wire [2:0]c;
    bcd_fadd bcd_1(a[3:0],b[3:0],cin,c[0],sum[3:0]);
    bcd_fadd bcd_2(a[7:4],b[7:4],c[0],c[1],sum[7:4]);
    bcd_fadd bcd_3(a[11:8],b[11:8],c[1],c[2],sum[11:8]);
    bcd_fadd bcd_4(a[15:12],b[15:12],c[2],cout,sum[15:12]);
endmodule